Viterbi IP Core User Guide

ID 683280
Date 11/06/2017
Public
Document Table of Contents
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3.5.2. Global Signals

Signal Name Description
clk The main system clock. The whole MegaCore function operates on the rising edge of clk.
reset Reset. The entire decoder is asynchronously reset when reset is asserted high. The reset signal resets the entire system. You must deassert the reset signal synchronously with respect to the rising edge of clk.