Viterbi IP Core User Guide

ID 683280
Date 11/06/2017
Public
Document Table of Contents
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3.5. Viterbi IP Core Interfaces and Signals

The Viterbi Avalon-ST interface supports backpressure, which is a flow control mechanism, where a sink can indicate to a source to stop sending data.

The ready latency on the Avalon-ST input interface is 1.

You may achieve a higher clock rate by driving the source ready signal source_rdy of the Viterbi high, and not connecting the sink ready signal sink_rdy.