AN 806: Hierarchical Partial Reconfiguration Tutorial: for Intel® Arria® 10 GX FPGA Development Board

ID 683278
Date 2/04/2021
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Hierarchical Partial Reconfiguration Tutorial for Intel Arria® 10 GX FPGA Development Board

Updated for:
Intel® Quartus® Prime Design Suite 20.3
This application note demonstrates transforming a simple design into a hierarchically partially reconfigurable design, and implementing the design on the Intel Arria® 10 GX FPGA development board.

Hierarchical partial reconfiguration (HPR) is an extension of the traditional partial reconfiguration (PR), where you contain a PR region within another PR region. You can create multiple personas for both the child and parent partitions. You nest the child partitions within their parent partitions. Reconfiguring a parent partition does not impact the operation in the static region, but replaces the child partitions of the parent region with default child partition personas. This methodology is effective in systems where multiple functions time-share the same FPGA device resources.

Partial reconfiguration provides the following advancements to a flat design:
  • Allows run-time design reconfiguration
  • Increases scalability of the design
  • Reduces system down-time
  • Supports dynamic time-multiplexing functions in the design
  • Lowers cost and power consumption through efficient use of board space

Implementation of this reference design requires basic familiarity with the Intel® Quartus® Prime FPGA implementation flow and knowledge of the primary Intel® Quartus® Prime project files. This tutorial uses the Intel Arria® 10 GX FPGA development board on the bench, outside of the PCIe* slot in your workstation.

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