AN 806: Hierarchical Partial Reconfiguration Tutorial: for Intel® Arria® 10 GX FPGA Development Board

ID 683278
Date 2/04/2021
Public

Step 7: Creating Revisions

The PR design flow uses the project revisions feature in the Intel® Quartus® Prime software. You designate your initial design is the base revision, where you define the static region boundaries and reconfigurable regions on the FPGA.

From this base revision, you create other revisions each implementation of the PR region. All PR implementation revisions must use the same top-level placement and routing results from the base revision.

To compile the PR design, you must create a PR implementation revision of the correct type for each PR persona. The following revision types are available:

  • Partial Reconfiguration - Base
  • Partial Reconfiguration - Persona Implementation

The following table lists the revision name and the revision type for each of the revisions you create in this tutorial:

Table 3.  Revision Names and Types
Revision Name Revision Type
blinking_led.qsf Partial Reconfiguration - Base
hpr_child_default.qsf Partial Reconfiguration - Persona Implementation
hpr_child_slow.qsf Partial Reconfiguration - Persona Implementation
hpr_child_empty.qsf Partial Reconfiguration - Persona Implementation
hpr_parent_slow_child_default.qsf Partial Reconfiguration - Persona Implementation
hpr_parent_slow_child_slow.qsf Partial Reconfiguration - Persona Implementation
Table 4.  Parent and Child Persona Revisions
Revision Name Parent Persona Behavior Child Persona Behavior
hpr_child_default.qsf Fast blinking Fast blinking
hpr_child_slow.qsf Fast blinking Slow blinking
hpr_child_empty.qsf Fast Blinking No blinking (always ON)
hpr_parent_slow_child_default.qsf Slow blinking Fast blinking
hpr_parent_slow_child_slow.qsf Slow blinking Slow blinking

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