AN 806: Hierarchical Partial Reconfiguration Tutorial: for Intel® Arria® 10 GX FPGA Development Board

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ID 683278
Date 2/04/2021
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Document Table of Contents
Document Table of Contents x
Hierarchical Partial Reconfiguration Tutorial for Intel Arria® 10 GX FPGA Development Board
Hierarchical Partial Reconfiguration Tutorial for Intel Arria® 10 GX FPGA Development Board x
Reference Design Requirements Reference Design Overview Reference Design Files Reference Design Walkthrough Document Revision History for Hierarchical Partial Reconfiguration Tutorial for Intel Arria® 10 GX FPGA Development Board
Reference Design Walkthrough x
Step 1: Getting Started Step 2: Creating a Child Level Sub-module Step 3: Creating Design Partitions Step 4: Allocating Placement and Routing Region for PR Partitions Step 5: Adding the Partial Reconfiguration Controller IP Step 6: Defining Personas Step 7: Creating Revisions Step 8: Compiling the Base Revision Step 9: Preparing the PR Implementation Revisions for Parent PR Partition Step 10: Preparing the PR Implementation Revisions for Child PR Partitions Step 11: Programming the Board Modifying an Existing Persona Adding a New Persona to the Design
Step 5: Adding the Partial Reconfiguration Controller IP x
Updating the Top-Level Design
Step 7: Creating Revisions x
Setting the Base Revision Type Creating Implementation Revisions
Step 11: Programming the Board x
Programming the Child PR Region Troubleshooting PR Programming Errors
Hierarchical Partial Reconfiguration Tutorial for Intel Arria® 10 GX FPGA Development Board

Programming the Child PR Region

You must ensure that you program the correct child persona to match the parent persona.
Running the prpof_id_mif_gen.tcl script before and after the base revision compile checks for incompatible bitstreams for Intel Arria® 10 devices, and outputs a PR_ERROR message for incorrect bitstreams. The following errors are possible unless you run the scripts as the tutorial describes:
  • Successful PR programming, but corrupted FPGA functionality
  • Unsuccessful PR programming, and corrupted FPGA functionality
If you wish to reprogram a child PR region on the FPGA, ensure that the child PR .rbf generates from an implementation revision compile whose parent PR persona matches the persona currently on the FPGA. For example, when you program the base blinking_led.sof onto the FPGA, the parent PR persona is default. The child PR persona is default as well. To change the child PR persona to the slow persona, you have the choice of using the following bitstreams:
  1. hpr_child_slow.pr_parent_partition.pr_partition.rbf
  2. hpr_parent_slow_child_slow.pr_parent_partition.pr_partition.rbf
In this case, you must choose hpr_child_slow.pr_parent_partition.pr_partition.rbf , as this file is generated by an implementation revision that has the default parent persona. Choosing hpr_parent_slow_child_slow.pr_parent_partition.pr_partition.rbf results in unsuccessful PR programming, corrupted FPGA functionality, or both.
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