AN 806: Hierarchical Partial Reconfiguration Tutorial: for Intel® Arria® 10 GX FPGA Development Board

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ID 683278
Date 2/04/2021
Public
Document Table of Contents
Document Table of Contents x
Hierarchical Partial Reconfiguration Tutorial for Intel Arria® 10 GX FPGA Development Board
Hierarchical Partial Reconfiguration Tutorial for Intel Arria® 10 GX FPGA Development Board x
Reference Design Requirements Reference Design Overview Reference Design Files Reference Design Walkthrough Document Revision History for Hierarchical Partial Reconfiguration Tutorial for Intel Arria® 10 GX FPGA Development Board
Reference Design Walkthrough x
Step 1: Getting Started Step 2: Creating a Child Level Sub-module Step 3: Creating Design Partitions Step 4: Allocating Placement and Routing Region for PR Partitions Step 5: Adding the Partial Reconfiguration Controller IP Step 6: Defining Personas Step 7: Creating Revisions Step 8: Compiling the Base Revision Step 9: Preparing the PR Implementation Revisions for Parent PR Partition Step 10: Preparing the PR Implementation Revisions for Child PR Partitions Step 11: Programming the Board Modifying an Existing Persona Adding a New Persona to the Design
Step 5: Adding the Partial Reconfiguration Controller IP x
Updating the Top-Level Design
Step 7: Creating Revisions x
Setting the Base Revision Type Creating Implementation Revisions
Step 11: Programming the Board x
Programming the Child PR Region Troubleshooting PR Programming Errors
Hierarchical Partial Reconfiguration Tutorial for Intel Arria® 10 GX FPGA Development Board

Step 1: Getting Started

To copy the reference design files to your working environment and compile the blinking_led flat design:
  1. Create a a10_pcie_devkit_blinking_led_hpr directory in your working environment.
  2. Copy the downloaded tutorials/a10_pcie_devkit_blinking_led_hpr/flat sub-folder to the a10_pcie_devkit_blinking_led_hpr directory.
  3. In the Intel® Quartus® Prime Pro Edition software, click File > Open Project and select blinking_led.qpf.
  4. To compile the flat design, click Processing > Start Compilation.
Level Two Title