AN 907: Enabling 5G Wireless Acceleration in FlexRAN: for the Intel® FPGA Programmable Acceleration Card N3000

ID 683275
Date 9/10/2020
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2.2. 5G Channel Coder

Send and receive code blocks for the encoder and decoder over PCIe to or from the host using the descriptor format defined in the Data Plane Development Kit (DPDK) and the baseband device. Contact Intel for the descriptor format.

The channel coders queue and process these blocks based on the load balancing decisions.

Figure 4. 5G Channel Coder

The downlink FEC accelerator consists of the 5G LDPC-V transmitter and the uplink FEC accelerator consists of the 5G LDPC-V receiver. The input to the downlink FEC accelerator is 32-bit data and the output data is 32-bit wide. For more information on the 5G LDPC-V transmitter and receiver, refer to the 5G LDPC-V Intel FPGA IP User Guide.

Figure 5. Transmitter SignalsThis figure does not show the Avalon streaming interface signals
Figure 6. Receiver SignalsThis figure does not show the Avalon streaming interface signals

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