AN 907: Enabling 5G Wireless Acceleration in FlexRAN: for the Intel® FPGA Programmable Acceleration Card N3000

ID 683275
Date 9/10/2020
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2.2.1. 5G Channel Coder Throughput

The Intel FPGA PAC N3000 5G channel coder accelerator contains two encoders and one decoder. The throughput depends on the traffic model.

For a single encoder, the clock rate, code block size (base graph number, lifting factor), code rate affect the throughput.

Figure 7. Downlink throughput for BG1The figure shows the downlink throughput with different parameters for BG1 (2 encoder engines).
Figure 8. Downlink throughput for BG2The figure shows the downlink throughput for BG2 with different parameters (2 encoder engines).

For a single decoder, the clock rate, code block size (base graph number, lifting factor), code rate, and literation number affect the throughput.

Figure 9. Uplink throughput for BG1The figure shows the uplink throughput with different parameters for BG1 (iteration number is 6).
Figure 10. Uplink throughput for BG2The figure shows the uplink throughput with different parameters for BG2 (iteration number is 6).

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