Intel® Quartus® Prime Pro Edition User Guide: Design Compilation

ID 683236
Date 11/03/2021

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2.7. Reducing Static Timing Analysis Time

If you are performing timing-driven synthesis, the Intel® Quartus® Prime software runs the Timing Analyzer during Analysis and Synthesis.

The Intel® Quartus® Prime Fitter also runs the Timing Analyzer during placement and routing. If there are incorrect constraints in the Synopsys* Design Constraints File (.sdc), the Intel® Quartus® Prime software may spend unnecessary time processing constraints several times.

  • If you do not specify false paths and multicycle paths in your design, the Timing Analyzer may analyze paths that are not relevant to your design.
  • If you redefine constraints in the .sdc files, the Timing Analyzer may spend additional time processing them. To avoid this situation, look for indications that Synopsis design constraints are being redefined in the compilation messages, and update the .sdc file.
  • Ensure that you provide the correct timing constraints to your design, because the software cannot assume design intent, such as which paths to consider as false paths or multicycle paths. When you specify these assignments correctly, the Timing Analyzer skips analysis for those paths, and the Fitter does not spend additional time optimizing those paths.