Intel® Quartus® Prime Pro Edition User Guide: Design Compilation
ID
683236
Date
11/03/2021
Public
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1.1. Compilation Overview
1.2. Using the Compilation Dashboard
1.3. Design Synthesis
1.4. Design Place and Route
1.5. Incremental Optimization Flow
1.6. Fast Forward Compilation Flow
1.7. Full Compilation Flow
1.8. Exporting Compilation Results
1.9. Integrating Other EDA Tools
1.10. Synthesis Language Support
1.11. Compiler Optimization Techniques
1.12. Synthesis Settings Reference
1.13. Fitter Settings Reference
1.14. Design Compilation Revision History
1.8.1. Exporting a Version-Compatible Compilation Database
1.8.2. Importing a Version-Compatible Compilation Database
1.8.3. Creating a Design Partition
1.8.4. Exporting a Design Partition
1.8.5. Reusing a Design Partition
1.8.6. Viewing Quartus Database File Information
1.8.7. Clearing Compilation Results
2.1. Factors Affecting Compilation Results
2.2. Compilation Time Advisor
2.3. Strategies to Reduce the Overall Compilation Time
2.4. Reducing Synthesis Time and Synthesis Netlist Optimization Time
2.5. Reducing Placement Time
2.6. Reducing Routing Time
2.7. Reducing Static Timing Analysis Time
2.8. Setting Process Priority
2.9. Reducing Compilation Time Revision History
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1. Design Compilation
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Intel® Quartus® Prime Design Suite 21.3 |
The Intel® Quartus® Prime Compiler synthesizes, places, and routes your design before generating device programming files. The Compiler supports a variety of high-level, HDL, and schematic design entry methods. The modules of the Compiler include IP Generation, Analysis & Synthesis, Fitter, Timing Analyzer, and Assembler.
Compilation Dashboard
The Intel® Quartus® Prime Pro Edition version of the Compiler supports these advanced features:
- Supports Intel® Arria® 10, Intel® Cyclone® 10 GX, Intel® Stratix® 10, and Intel® Agilex™ devices.
- Incremental Fitter optimization—analyze and optimize after each Fitter stage to maximize performance and shorten total compilation time.
- Hyper-Aware Design Flow—use Hyper-Retiming and Fast Forward compilation for the highest performance in Intel® Stratix® 10 and Intel® Agilex™ devices.
- Partial Reconfiguration—dynamic reconfiguration of a portion of the FPGA, while the remaining FPGA continues to function.
- Block-Based Design Flows—preservation and reuse of design blocks.
- Compilation Overview
- Using the Compilation Dashboard
- Design Synthesis
- Design Place and Route
- Incremental Optimization Flow
- Fast Forward Compilation Flow
- Full Compilation Flow
- Exporting Compilation Results
- Integrating Other EDA Tools
- Synthesis Language Support
- Compiler Optimization Techniques
- Synthesis Settings Reference
- Fitter Settings Reference
- Design Compilation Revision History