Intel® Quartus® Prime Pro Edition User Guide: Design Compilation

Download PDF
ID 683236
Date 11/03/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. Design Compilation 2. Reducing Compilation Time 3. Intel® Quartus® Prime Pro Edition User Guide Design Compilation Archives A. Intel® Quartus® Prime Pro Edition User Guides
1. Design Compilation x
1.1. Compilation Overview 1.2. Using the Compilation Dashboard 1.3. Design Synthesis 1.4. Design Place and Route 1.5. Incremental Optimization Flow 1.6. Fast Forward Compilation Flow 1.7. Full Compilation Flow 1.8. Exporting Compilation Results 1.9. Integrating Other EDA Tools 1.10. Synthesis Language Support 1.11. Compiler Optimization Techniques 1.12. Synthesis Settings Reference 1.13. Fitter Settings Reference 1.14. Design Compilation Revision History
1.1. Compilation Overview x
1.1.1. Compilation Flows 1.1.2. Compilation Hierarchy
1.3. Design Synthesis x
1.3.1. Running Synthesis 1.3.2. Viewing Synthesis Reports
1.3.1. Running Synthesis x
1.3.1.1. Preserving Registers During Synthesis 1.3.1.2. Preserving Signals for Monitoring and Debugging
1.4. Design Place and Route x
1.4.1. Running the Fitter 1.4.2. Viewing Fitter Reports
1.4.1. Running the Fitter x
1.4.1.1. Fitter Commands 1.4.1.2. Enabling Physical Synthesis Optimization
1.4.2. Viewing Fitter Reports x
1.4.2.1. Plan Stage Reports 1.4.2.2. Place Stage Reports 1.4.2.3. Route Stage Reports 1.4.2.4. Retime Stage Reports 1.4.2.5. Finalize Stage Reports
1.4.2.2. Place Stage Reports x
1.4.2.2.1. Global Signal Visualization Report
1.4.2.3. Route Stage Reports x
1.4.2.3.1. Global Router Wire Utilization Map Report
1.5. Incremental Optimization Flow x
1.5.1. Concurrent Analysis During Synthesis or Fitting 1.5.2. Analyzing Compiler Snapshots 1.5.3. Validating Periphery (I/O) after the Plan Stage
1.5.2. Analyzing Compiler Snapshots x
1.5.2.1. Running Snapshot Viewer
1.5.2.1. Running Snapshot Viewer x
1.5.2.1.1. Analyzing Failing Paths with Snapshot Viewer 1.5.2.1.2. Analyzing Clocking with Snapshot Viewer 1.5.2.1.3. Analyzing High Fan-out Nets with Snapshot Viewer 1.5.2.1.4. Validating Timing Constraints with Snapshot Viewer 1.5.2.1.5. Analyzing Congestion with Snapshot Viewer
1.6. Fast Forward Compilation Flow x
1.6.1. Step 1: Run Register Retiming 1.6.2. Step 2: Review Retiming Results 1.6.3. Step 3: Run Fast Forward Compile 1.6.4. Step 4: Review Fast Forward Results 1.6.5. Step 5: Implement Fast Forward Recommendations 1.6.6. Retiming Restrictions and Workarounds
1.6.2. Step 2: Review Retiming Results x
1.6.2.1. Locate Critical Chains
1.6.3. Step 3: Run Fast Forward Compile x
1.6.3.1. Fast Forward Compile By Hierarchy 1.6.3.2. HyperFlex Settings
1.6.4. Step 4: Review Fast Forward Results x
1.6.4.1. Clock Fmax Summary Report 1.6.4.2. Fast Forward Details Report
1.8. Exporting Compilation Results x
1.8.1. Exporting a Version-Compatible Compilation Database 1.8.2. Importing a Version-Compatible Compilation Database 1.8.3. Creating a Design Partition 1.8.4. Exporting a Design Partition 1.8.5. Reusing a Design Partition 1.8.6. Viewing Quartus Database File Information 1.8.7. Clearing Compilation Results
1.8.6. Viewing Quartus Database File Information x
1.8.6.1. QDB File Attribute Types
1.9. Integrating Other EDA Tools x
1.9.1. Generating a VQM Netlist for other EDA Tools
1.10. Synthesis Language Support x
1.10.1. Verilog and SystemVerilog Synthesis Support 1.10.2. VHDL Synthesis Support
1.10.1. Verilog and SystemVerilog Synthesis Support x
1.10.1.1. Verilog HDL Input Settings (Settings Dialog Box) 1.10.1.2. Design Libraries 1.10.1.3. Verilog HDL Configuration 1.10.1.4. Initial Constructs and Memory System Tasks 1.10.1.5. Verilog HDL Macros
1.10.1.3. Verilog HDL Configuration x
1.10.1.3.1. Hierarchical Design Configurations
1.10.2. VHDL Synthesis Support x
1.10.2.1. VHDL Input Settings (Settings Dialog Box) 1.10.2.2. VHDL Standard Libraries and Packages 1.10.2.3. VHDL wait Constructs 1.10.2.4. VHDL-2019 Conditional Analysis Tool Directives
1.11. Compiler Optimization Techniques x
1.11.1. Optimization Modes 1.11.2. Allow Register Retiming 1.11.3. Automatic Gated Clock Conversion 1.11.4. Enable Intermediate Fitter Snapshots 1.11.5. Fast Preserve Option 1.11.6. Fractal Synthesis Optimization
1.11.6. Fractal Synthesis Optimization x
1.11.6.1. Enabling or Disabling Fractal Synthesis
1.12. Synthesis Settings Reference x
1.12.1. Advanced Synthesis Settings
2. Reducing Compilation Time x
2.1. Factors Affecting Compilation Results 2.2. Compilation Time Advisor 2.3. Strategies to Reduce the Overall Compilation Time 2.4. Reducing Synthesis Time and Synthesis Netlist Optimization Time 2.5. Reducing Placement Time 2.6. Reducing Routing Time 2.7. Reducing Static Timing Analysis Time 2.8. Setting Process Priority 2.9. Reducing Compilation Time Revision History
2.3. Strategies to Reduce the Overall Compilation Time x
2.3.1. Running the ECO Compilation Flow 2.3.2. Enabling Multi-Processor Compilation 2.3.3. Using Block-Based Compilation
2.4. Reducing Synthesis Time and Synthesis Netlist Optimization Time x
2.4.1. Settings to Reduce Synthesis Time and Synthesis Netlist Optimization Time 2.4.2. Use Appropriate Coding Style to Reduce Synthesis Time
2.5. Reducing Placement Time x
2.5.1. Placement Effort Multiplier Settings
2.6. Reducing Routing Time x
2.6.1. Identifying Routing Congestion with the Chip Planner
2.6.1. Identifying Routing Congestion with the Chip Planner x
2.6.1.1. Areas with Routing Congestion 2.6.1.2. Congestion due to HDL Coding style
1. Design Compilation
2. Reducing Compilation Time
3. Intel® Quartus® Prime Pro Edition User Guide Design Compilation Archives
A. Intel® Quartus® Prime Pro Edition User Guides

1.8. Exporting Compilation Results

The Intel® Quartus® Prime Compiler writes the results to a set of database files. You can run a command to export the compilation results database as a single Quartus Database File (.qdb).

After running design compilation, the exported .qdb file contains the data to reproduce similar compilation results in another project, or in a later software version. You can export your project's compilation results database for import to another project or migration to a later Intel® Quartus® Prime software version.

You can export the .qdb for your entire project or for a design partition that you define in your project. When migrating the database for an entire project, you can export the compilation database in a version-compatible format to ensure compatibility for import to a later software version. Although you cannot directly read the contents of the .qdb file after export, you can view attributes of the database file in the Quartus Database File Viewer.

Table 16.  Exporting Compilation Results
To Export Compilation Results For Method Description
Complete Design Click Project > Export Design Saves compilation results for the current project revision in a version-compatible Quartus database file (.qdb) that you can import to another project or migrate to a later version of the Intel® Quartus® Prime software. You can export the results for the synthesized or final compilation snapshot.
Note: Not supported for Intel® Agilex™ devices.
Design Partition Click Project > Export Design Partition Saves compilation results for a design partition as a Partition Database File (.qdb) that you can import to another project using the same version of the Intel® Quartus® Prime software. You can export the results for the synthesized or final compilation snapshot.
Related Information
Level Two Title