Intel® Quartus® Prime Pro Edition User Guide: Design Compilation

ID 683236
Date 11/03/2021
Public

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Document Table of Contents

2.9. Reducing Compilation Time Revision History

Document Version Intel® Quartus® Prime Version Changes
2021.11.03 21.3
  • Made minor update to step 1 in Using Block-Based Compilation.
2021.10.04 21.3
  • Removed "Disabling the Register Power-up Initialization".
2021.03.29 21.1
  • Support for Rapid Recompile has been removed, resulting in the following changes:
    • Removed reference to Rapid Recompile from "Strategies to Reduce the Overall Compilation Time".
    • Removed "Running Rapid Recompile" topic.
2020.09.28 20.3
  • Added reference to ECO Compilation flow.
2019.11.11 19.3
  • Added support for Fast Preserve option to "Using Block-Based Compilation" topic.
2019.09.30 19.3
  • Added support for Intel® Agilex™ devices throughout.
2019.07.02 19.1 Added the Using the No-Register Initialization Flow topic.
2018.10.19 18.1
  • Described dependency of Rapid Recompile on Enable Intermediate Fitter Snapshots option.
2017.11.06 17.1
  • Added topic: Using Block-Based Compilation.
Date Version Changes
2017.05.08 17.0.0
  • Clarified impact of multiprocessor compilation on fit quality.
  • Removed reference to deprecated Fitter Effort Logic Option.
  • Removed section: Preserving Routing with Incremental Compilation.
2016.10.31 16.1.0
  • Implemented Intel rebranding.
2016.05.02 16.0.0
  • Corrected typo in Using Parallel Compilation with Multiple Processors.
  • Removed information about deprecated physical synthesis options.
2015.11.02 15.1.0 Changed instances of Quartus II to Intel® Quartus® Prime .
2014.12.15 14.1.0
  • Updated location of Fitter Settings, Analysis & Synthesis Settings, and Physical Synthesis Optimizations to Compiler Settings.
  • Added information about Rapid Recompile feature.

2014.08.18

14.0a10.0

Added restriction about smart compilation in Arria 10 devices.

June 2014 14.0.0 Updated format.
May 2013 13.0.0 Removed the “Limit to One Fitting Attempt”, “Using Early Timing Estimation”, “Final Placement Optimizations”, and “Using Rapid Recompile” sections.

Updated “Placement Effort Multiplier Settings” section.

Updated “Identifying Routing Congestion in the Chip Planner” section.

General editorial changes throughout the chapter.

June 2012 12.0.0 Removed survey link.
November 2011 11.0.1 Template update.
May 2011 11.0.0
  • Updated “Using Parallel Compilation with Multiple Processors”.
  • Updated “Identifying Routing Congestion in the Chip Planner”.
  • General editorial changes throughout the chapter.
December 2010 10.1.0
  • Template update.
  • Added details about peak and average interconnect usage.
  • Added new section “Reducing Static Timing Analysis Time”.
  • Minor changes throughout chapter.
July 2010 10.0.0 Initial release.