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1.1. Compilation Overview
1.2. Using the Compilation Dashboard
1.3. Design Synthesis
1.4. Design Place and Route
1.5. Incremental Optimization Flow
1.6. Fast Forward Compilation Flow
1.7. Full Compilation Flow
1.8. Exporting Compilation Results
1.9. Integrating Other EDA Tools
1.10. Synthesis Language Support
1.11. Compiler Optimization Techniques
1.12. Synthesis Settings Reference
1.13. Fitter Settings Reference
1.14. Design Compilation Revision History
1.8.1. Exporting a Version-Compatible Compilation Database
1.8.2. Importing a Version-Compatible Compilation Database
1.8.3. Creating a Design Partition
1.8.4. Exporting a Design Partition
1.8.5. Reusing a Design Partition
1.8.6. Viewing Quartus Database File Information
1.8.7. Clearing Compilation Results
2.1. Factors Affecting Compilation Results
2.2. Compilation Time Advisor
2.3. Strategies to Reduce the Overall Compilation Time
2.4. Reducing Synthesis Time and Synthesis Netlist Optimization Time
2.5. Reducing Placement Time
2.6. Reducing Routing Time
2.7. Reducing Static Timing Analysis Time
2.8. Setting Process Priority
2.9. Reducing Compilation Time Revision History
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1.4.2.2. Place Stage Reports
The Place stage reports describe all device resources the Fitter allocates during logic placement, as well as use of Logic Lock regions and global and other fast signals.
Figure 7. Place Stage Reports