Intel® Programmable Acceleration Card (PAC) with Intel® Arria® 10 GX FPGA Data Sheet

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ID 683226
Date 10/26/2020
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Overview 3. System Compatibility 4. Mechanical Information 5. Thermal Specifications 6. FPGA Interface Manager 7. Board Management Controller 8. PLDM Commands for the Board Management Controller A. Regulatory Information B. References C. Revision History
2. Overview x
2.1. Views of the Intel® PAC with Intel® Arria® 10 GX FPGA 2.2. Overview of Product Features
2.2. Overview of Product Features x
2.2.1. Intel® Arria® 10 GX FPGA 2.2.2. On-Board Memory 2.2.3. Interfaces and Dimensions 2.2.4. Software 2.2.5. Power 2.2.6. CPLD 2.2.7. QSFP+ 2.2.8. Control and Support
2.2.8. Control and Support x
2.2.8.1. PCIe Overview 2.2.8.2. Board Management Controller Overview
4. Mechanical Information x
4.1. Air Duct Disassembly
5. Thermal Specifications x
5.1. Thermal Test Performance Results
6. FPGA Interface Manager x
6.1. Updating the FIM
7. Board Management Controller x
7.1. Features 7.2. Device Peripheral Table 7.3. Updating the BMC Configuration and Firmware
7.1. Features x
7.1.1. BMC Voltage and Thermal Handling
8. PLDM Commands for the Board Management Controller x
8.1. I2C/SMBus Address 8.2. Supported SMBus Commands 8.3. Supported MCTP Commands 8.4. Supported PLDM Commands 8.5. Defined Platform Descriptor Records 8.6. Sensor and Threshold Information
8.3. Supported MCTP Commands x
8.3.1. MCTP Control Messages
8.4. Supported PLDM Commands x
8.4.1. PLDM Base Specification Commands 8.4.2. PLDM for Platform Monitoring and Control Specification Commands
1. Introduction
2. Overview
3. System Compatibility
4. Mechanical Information
5. Thermal Specifications
6. FPGA Interface Manager
7. Board Management Controller
8. PLDM Commands for the Board Management Controller
A. Regulatory Information
B. References
C. Revision History

7. Board Management Controller

A board management controller (BMC) resides on the Intel® PAC with Intel® Arria® 10 GX FPGA.


Section Content
Features
Device Peripheral Table
Updating the BMC Configuration and Firmware

Level Two Title