AN-731: Simultaneous Switching Noise Guidelines for Intel® Cyclone® 10 LP, Cyclone® IV, and Cyclone® III Devices

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ID 683204
Date 11/06/2017
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Document Table of Contents
Document Table of Contents x
Simultaneous Switching Noise Guidelines for Intel® Cyclone® 10 LP, Cyclone® IV, and Cyclone® III Devices
Simultaneous Switching Noise Guidelines for Intel® Cyclone® 10 LP, Cyclone® IV, and Cyclone® III Devices x
External Clock Inputs Guidelines I/O Restriction Guidelines Single-Ended Clock Input Pad Placement Guideline Document Revision History for AN-731: Simultaneous Switching Noise Guidelines for Intel® Cyclone® 10 LP, Cyclone® IV, and Cyclone® III Devices
External Clock Inputs Guidelines x
Victim Clock Pin Assignments External Single-Ended Clock Input SSN Requirements Effects of I/O Termination Effect of Slow Aggressor Signal Slew Rate on SSN Effect of Fast Slew Rate of Victim Clock on SSN
Simultaneous Switching Noise Guidelines for Intel® Cyclone® 10 LP, Cyclone® IV, and Cyclone® III Devices

Effect of Fast Slew Rate of Victim Clock on SSN

Crosstalk or SSN on power and ground can induce a glitch or jitter on the victim clock input signal. Increasing the ramp time (V/ns) of the victim clock input signal will mitigate this affect. Fast rise and fall edges reduce the time the clock signal is above VIH and below VIL and can push out the glitch from VIH or VIL zone such that it no longer affects the clock and reset signals.

Figure 6.  Benefit of Faster Slew Rate on Victim Clock Input


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