AN-731: Simultaneous Switching Noise Guidelines for Intel® Cyclone® 10 LP, Cyclone® IV, and Cyclone® III Devices

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ID 683204
Date 11/06/2017
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Document Table of Contents
Document Table of Contents x
Simultaneous Switching Noise Guidelines for Intel® Cyclone® 10 LP, Cyclone® IV, and Cyclone® III Devices
Simultaneous Switching Noise Guidelines for Intel® Cyclone® 10 LP, Cyclone® IV, and Cyclone® III Devices x
External Clock Inputs Guidelines I/O Restriction Guidelines Single-Ended Clock Input Pad Placement Guideline Document Revision History for AN-731: Simultaneous Switching Noise Guidelines for Intel® Cyclone® 10 LP, Cyclone® IV, and Cyclone® III Devices
External Clock Inputs Guidelines x
Victim Clock Pin Assignments External Single-Ended Clock Input SSN Requirements Effects of I/O Termination Effect of Slow Aggressor Signal Slew Rate on SSN Effect of Fast Slew Rate of Victim Clock on SSN
Simultaneous Switching Noise Guidelines for Intel® Cyclone® 10 LP, Cyclone® IV, and Cyclone® III Devices

External Single-Ended Clock Input SSN Requirements

You can assign ground on the original differential clock pair, when you use the external clock input as a single-ended clock. As shown in the following figure, the differential signal pair in the package, is laid out as differential, with a value of 100 Ω. It ensures that the original differential clock pair has a strong coupling structure.

Intel recommends that you do not assign any other clock signal or normal I/O signal on the original differential clock pair, if you assign an external clock input as a single-ended clock. This signal can cause large coupling noise on the single-ended clock input signal.

Figure 3. Package Design Example for a Differential Clock Input Signal Pair


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