AN-731: Simultaneous Switching Noise Guidelines for Intel® Cyclone® 10 LP, Cyclone® IV, and Cyclone® III Devices

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ID 683204
Date 11/06/2017
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Document Table of Contents x
Simultaneous Switching Noise Guidelines for Intel® Cyclone® 10 LP, Cyclone® IV, and Cyclone® III Devices
Simultaneous Switching Noise Guidelines for Intel® Cyclone® 10 LP, Cyclone® IV, and Cyclone® III Devices x
External Clock Inputs Guidelines I/O Restriction Guidelines Single-Ended Clock Input Pad Placement Guideline Document Revision History for AN-731: Simultaneous Switching Noise Guidelines for Intel® Cyclone® 10 LP, Cyclone® IV, and Cyclone® III Devices
External Clock Inputs Guidelines x
Victim Clock Pin Assignments External Single-Ended Clock Input SSN Requirements Effects of I/O Termination Effect of Slow Aggressor Signal Slew Rate on SSN Effect of Fast Slew Rate of Victim Clock on SSN
Simultaneous Switching Noise Guidelines for Intel® Cyclone® 10 LP, Cyclone® IV, and Cyclone® III Devices

Victim Clock Pin Assignments

Assignments for pins adjacent to the clock input pin affect SSN. SSN is directly proportional to the mutual inductance of the ground path.
Figure 2. Single-Ended Clock Input Ground Balls Surrounding Victim Clock Input Signals
  • As shown in (a), you can reduce the effect of SSN by assigning all of the ground balls surrounding the single-ended clock.
  • As shown in (b), if you cannot assign all of the ground balls, then you must try to have a minimum of four ground balls around the single-ended clock path.


The ground balls decrease the mutual inductance of the victim single-ended clock and block crosstalk from adjacent potential aggressor I/O signals.

Intel recommends that you do not assign any other clock signal or normal I/O signal on the original differential clock pair. This signal can cause large coupling noise on the single-ended clock input signal.

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