Simultaneous Switching Noise Guidelines for Intel® Cyclone® 10 LP, Cyclone® IV, and Cyclone® III Devices

External Clock Inputs Guidelines I/O Restriction Guidelines Single-Ended Clock Input Pad Placement Guideline Document Revision History for AN-731: Simultaneous Switching Noise Guidelines for Intel® Cyclone® 10 LP, Cyclone® IV, and Cyclone® III Devices

Victim Clock Pin Assignments External Single-Ended Clock Input SSN Requirements Effects of I/O Termination Effect of Slow Aggressor Signal Slew Rate on SSN Effect of Fast Slew Rate of Victim Clock on SSN