AN-731: Simultaneous Switching Noise Guidelines for Intel® Cyclone® 10 LP, Cyclone® IV, and Cyclone® III Devices

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ID 683204
Date 11/06/2017
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Document Table of Contents
Document Table of Contents x
Simultaneous Switching Noise Guidelines for Intel® Cyclone® 10 LP, Cyclone® IV, and Cyclone® III Devices
Simultaneous Switching Noise Guidelines for Intel® Cyclone® 10 LP, Cyclone® IV, and Cyclone® III Devices x
External Clock Inputs Guidelines I/O Restriction Guidelines Single-Ended Clock Input Pad Placement Guideline Document Revision History for AN-731: Simultaneous Switching Noise Guidelines for Intel® Cyclone® 10 LP, Cyclone® IV, and Cyclone® III Devices
External Clock Inputs Guidelines x
Victim Clock Pin Assignments External Single-Ended Clock Input SSN Requirements Effects of I/O Termination Effect of Slow Aggressor Signal Slew Rate on SSN Effect of Fast Slew Rate of Victim Clock on SSN
Simultaneous Switching Noise Guidelines for Intel® Cyclone® 10 LP, Cyclone® IV, and Cyclone® III Devices

Effects of I/O Termination

Unterminated signals can cause signal reflection. These reflections can manifest themselves as crosstalk noise on the victim clock signal.

The reflected waveforms in the multi-aggressor signals will transmit back-and-forth and can cause crosstalk noise on the victim clock input signal and can have an effect on power and ground. As shown in Figure 4, terminating potential aggressor signals appropriately will reduce the possibility of degrading the victim clock signal quality and power and ground noise.

In Intel® Cyclone® 10 LP, Cyclone® IV, and Cyclone® III devices, signal I/O standard can be selected in terminated or un-terminated mode.

Figure 4. Reflection Due to Matched and Open Termination


Note:

I/O Standards with or without Termination:

  • Terminated I/O standards—SSTL, HSTL
  • Unterminated I/O standards—LVTTL, LVCMOS

As per JEDEC, the LVTTL and LVCMOS, PCI, and PCI-X I/O standards do not specify a recommended termination scheme.

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