AN 735: Altera Low Latency Ethernet 10G MAC IP Core Migration Guidelines

ID 683191
Date 5/04/2015

1.2.2. Generating 156.25 MHz and 312.5 MHz Clock

The core clock for Low Latency Ethernet 10G MAC uses 312.5 MHz clock. Therefore, you are required to provide an additional 312.5MHz clock source to the MAC.
  1. Instantiate a separate 312.5 MHz clock from any existing PLL in the design.
  2. Connect this clock source to tx_312_5_clk and rx_312_5_clk signals.
    Both clock signals can share the same clock source.

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