AN 735: Altera Low Latency Ethernet 10G MAC IP Core Migration Guidelines

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ID 683191
Date 5/04/2015
Public
Document Table of Contents
Document Table of Contents x
1. Altera Low Latency Ethernet 10G MAC IP Core Migration Guidelines
1. Altera Low Latency Ethernet 10G MAC IP Core Migration Guidelines x
1.1. Differences between 10GbE MAC IP Core and Low Latency Ethernet 10G MAC IP Core 1.2. Migration Flow 1.3. AN 735 Document Revision History
1.1. Differences between 10GbE MAC IP Core and Low Latency Ethernet 10G MAC IP Core x
1.1.1. Architecture Overview 1.1.2. Clock and Reset Scheme 1.1.3. Interface Signals
1.2. Migration Flow x
1.2.1. Instantiating Low Latency Ethernet MAC IP Core 1.2.2. Generating 156.25 MHz and 312.5 MHz Clock 1.2.3. Connecting the Low Latency Ethernet 10G MAC to Avalon-ST, Avalon-MM, and XGMII PHY Interfaces
1. Altera Low Latency Ethernet 10G MAC IP Core Migration Guidelines

1.3. AN 735 Document Revision History

Table 4.  Document Revision History
Date Version Changes
May 2015 2015.05.04 Initial release.
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