AN 735: Altera Low Latency Ethernet 10G MAC IP Core Migration Guidelines

ID 683191
Date 5/04/2015
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1.1.3. Interface Signals

There are several differences on the interface signals between 10GbE MAC IP core and Low Latency Ethernet 10G MAC IP core.

If the Low Latency Ethernet 10G MAC IP core with 64-bit Avalon-ST adapter, 64-bit Avalon-MM adapter, and 64-bit XGMII adapters are enabled, you may observe these additional signals in the IP core:

  • tx_312_5_clk
  • rx_312_5_clk
  • ecc_err_det_corr
  • ecc_err_det_uncorr

For the Low Latency Ethernet 10G MAC IP core instantiation without enabling any adapters, you may observe these signal names in the IP core:

  • tx_312_5_clk
  • rx_312_5_clk
  • ecc_err_det_corr
  • ecc_err_det_uncorr
  • 10-bit csr_address
  • 32-bit Avalon_st_tx_data
  • 2-bit Avalon_st_tx_empty
  • 32-bit Avalon_st_rx_data
  • 2-bit Avalon_st_rx_empty
  • 32-bit xgmii_tx_data
  • 4-bit xgmii_tx_control
  • 32-bit xgmii_rx_data
  • 4-bit xgmii_rx_control
Figure 6.  Interface Signal Differences for Low Latency Ethernet 10G MAC IP and 10GbE MAC IP core This figure shows the interface signal differences between the 10GbE MAC IP core and Low Latency Ethernet 10G MAC IP core. The differences between these two IP cores are highlighted in blue.


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