AN 735: Altera Low Latency Ethernet 10G MAC IP Core Migration Guidelines

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ID 683191
Date 5/04/2015
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Document Table of Contents
Document Table of Contents x
1. Altera Low Latency Ethernet 10G MAC IP Core Migration Guidelines
1. Altera Low Latency Ethernet 10G MAC IP Core Migration Guidelines x
1.1. Differences between 10GbE MAC IP Core and Low Latency Ethernet 10G MAC IP Core 1.2. Migration Flow 1.3. AN 735 Document Revision History
1.1. Differences between 10GbE MAC IP Core and Low Latency Ethernet 10G MAC IP Core x
1.1.1. Architecture Overview 1.1.2. Clock and Reset Scheme 1.1.3. Interface Signals
1.2. Migration Flow x
1.2.1. Instantiating Low Latency Ethernet MAC IP Core 1.2.2. Generating 156.25 MHz and 312.5 MHz Clock 1.2.3. Connecting the Low Latency Ethernet 10G MAC to Avalon-ST, Avalon-MM, and XGMII PHY Interfaces
1. Altera Low Latency Ethernet 10G MAC IP Core Migration Guidelines

1.1. Differences between 10GbE MAC IP Core and Low Latency Ethernet 10G MAC IP Core

Table below shows the general features supported by both the MAC IP cores. For full list of supported features, refer to its respective user guides.
Table 2.  Features of the 10GbE MAC IP core and Low Latency Ethernet 10G MAC IP
Features Low Latency Ethernet 10G MAC IP Core 10GbE MAC IP core
Multispeed operation (10M/100M/1G/10Gbps) Yes Yes
64-bits Avalon-Streaming (Avalon-ST) interface Yes Yes
32-bits Avalon-ST interface Yes —
64-bits XGMII PHY interface Yes Yes
32-bits XGMII PHY interface Yes —
GMII and MII PHY interface Yes Yes
Optional IEEE 1588v2 features Yes Yes
Optional statistic collections for transmit and receive datapaths Yes Yes
Optional ECC correction and detection Yes —
Compliant to IEEE 802.3 – 2008 specification Yes Yes
Two new additional features are available only in the Low Latency Ethernet 10G MAC IP core:
  • 32-bits Avalon-ST interface and 32-bit XGMII PHY interface for reduced pin count.
  • ECC correction and detection for all internal RAMs that reside in the MAC. This is to provide status on single bit data correction and multi bit error data detection in the RAM that is impacted by electrical or magnetic interference.

Section Content
Architecture Overview
Clock and Reset Scheme
Interface Signals

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