AN 735: Altera Low Latency Ethernet 10G MAC IP Core Migration Guidelines

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ID 683191
Date 5/04/2015
Public
Document Table of Contents
Document Table of Contents x
1. Altera Low Latency Ethernet 10G MAC IP Core Migration Guidelines
1. Altera Low Latency Ethernet 10G MAC IP Core Migration Guidelines x
1.1. Differences between 10GbE MAC IP Core and Low Latency Ethernet 10G MAC IP Core 1.2. Migration Flow 1.3. AN 735 Document Revision History
1.1. Differences between 10GbE MAC IP Core and Low Latency Ethernet 10G MAC IP Core x
1.1.1. Architecture Overview 1.1.2. Clock and Reset Scheme 1.1.3. Interface Signals
1.2. Migration Flow x
1.2.1. Instantiating Low Latency Ethernet MAC IP Core 1.2.2. Generating 156.25 MHz and 312.5 MHz Clock 1.2.3. Connecting the Low Latency Ethernet 10G MAC to Avalon-ST, Avalon-MM, and XGMII PHY Interfaces
1. Altera Low Latency Ethernet 10G MAC IP Core Migration Guidelines

1.2.3. Connecting the Low Latency Ethernet 10G MAC to Avalon-ST, Avalon-MM, and XGMII PHY Interfaces

After generating the synthesis file for the Low Latency Ethernet 10G MAC IP core, you can replace the existing 10GbE MAC IP core synthesis file (<user_specified_ip_filename> .v) with the newly generated Low Latency Ethernet 10G MAC synthesis file. Due to the differences in the signal names between both cores, you must make sure these signals are connected correctly to the user and PHY interfaces.

Table 3.   Differences in Signal Names for Low Latency Ethernet 10G MAC IP Core and 10GbE MAC IP CoreThis table lists the signal names in the Low Latency Ethernet 10G MAC IP core with all 64-bit MAC interface adapters enabled and its corresponding signals in the 10GbE MAC IP core.
Low Latency Ethernet 10G MAC IP Signal Names 10GbE MAC IP Core Signal Names
csr_clk csr_clk_clk
csr_rst_n csr_reset_reset_n
tx_156_25_clk tx_clk_clk
tx_rst_n tx_reset_reset_n
rx_156_25_clk rx_clk_clk
rx_rst_n rx_reset_reset_n
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