AN 710: Altera JESD204B MegaCore Function and ADI AD9680 Hardware Checkout Report

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ID 683170
Date 5/11/2015
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Document Table of Contents
Document Table of Contents x
1. Altera JESD204B IP Core and ADI AD9680 Hardware Checkout Report
1. Altera JESD204B IP Core and ADI AD9680 Hardware Checkout Report x
1.1. Hardware Requirements 1.2. Hardware Setup for Stratix V Advanced Systems Development Kit 1.3. Hardware Setup for Arria 10 FPGA Development Kit 1.4. Hardware Checkout Methodology 1.5. JESD204B IP Core and ADC Configurations 1.6. Test Results for Stratix V and Arria 10 FPGA 1.7. Test Result Comments 1.8. AN 710 Document Revision History
1.4. Hardware Checkout Methodology x
1.4.1. Receiver Data Link Layer 1.4.2. Receiver Transport Layer 1.4.3. Descrambling 1.4.4. Deterministic Latency (Subclass 1)
1.4.1. Receiver Data Link Layer x
1.4.1.1. Code Group Synchronization (CGS) 1.4.1.2. Initial Frame and Lane Synchronization
1. Altera JESD204B IP Core and ADI AD9680 Hardware Checkout Report

1.7. Test Result Comments

In each test case, the RX JESD204B IP core successfully initialize from CGS phase, ILA phase, and until user data phase. No data integrity issue is observed by the PRBS checker. For test case with LMF=411 and 412, the data rate is reduced to 6250 Mbps to limit the ADC sampling rate to 1250 Msps. The following table describes the scenarios where there is a difference in the data rate.

Table 11.  Sample Rate Implication for Test Case with LMF=411 and 412

Item

Scenario 1

Scenario 2

Remark

Data rate

12500 Mbps

6250Mbps

Data rate is within the operating condition of AD9680 device.

Link clock = data rate/40

312.5 MHz

156.25 MHz

Link clock frequency is determined by the data rate.

ADC sample clock must be ≤ ADC maximum sampling rate

2500 Msps

1250 Msps

Sample clock frequency in scenario 1 is beyond the operating condition of AD9680 device.

In deterministic measurement test case DL.3, the link clock count in the FPGA depends on the board layout and the LMFC offset value set in the ADC register. The link clock count varies by only one link clock when the FPGA and ADC are reset or power cycled. The link clock variation in the deterministic latency measurement is caused by word alignment, where the control characters fall into the next cycle of data some time after realignment. This makes the duration of ILAS phase longer by one link clock some time after reset or power cycle.

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