1.2. Hardware Setup for Stratix V Advanced Systems Development Kit
A Stratix V Advanced Systems Development Kit is used with the ADI AD9680 daughter card module 3 attached to the FMC connector on the development board.
- The AD9680 EVM derives power from 4.5 V power adaptor.
- The FPGA and ADC device clock is supplied by external clock source card through the SMA connectors on the AD9680 EVM.
- Both the FPGA and ADC device clock must be sourced from the same clock source card with two different frequencies, one for the FPGA and one for ADC.
- For subclass 1, the FPGA generates SYSREF for the JESD204B IP core as well as the AD9680 device.
The system-level diagram shows how the different modules connect in this design.
In this setup, where LMF=421, the data rate of transceiver lanes is 12.5 Gbps. An external clock source card provides 312.5 MHz clock to the FPGA and 1250 MHz sampling clock to AD9680 device.
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