AN 710: Altera JESD204B MegaCore Function and ADI AD9680 Hardware Checkout Report
ID
683170
Date
5/11/2015
Public
1.1. Hardware Requirements
1.2. Hardware Setup for Stratix V Advanced Systems Development Kit
1.3. Hardware Setup for Arria 10 FPGA Development Kit
1.4. Hardware Checkout Methodology
1.5. JESD204B IP Core and ADC Configurations
1.6. Test Results for Stratix V and Arria 10 FPGA
1.7. Test Result Comments
1.8. AN 710 Document Revision History
1.4. Hardware Checkout Methodology
The following section describes the test objectives, procedure, and the passing criteria. The test covers the following areas:
- Receiver data link layer
- Receiver transport layer
- Descrambling
- Deterministic latency (Subclass 1)