AN 710: Altera JESD204B MegaCore Function and ADI AD9680 Hardware Checkout Report

ID 683170
Date 5/11/2015
Public

1.4.2. Receiver Transport Layer

To check the data integrity of the payload data stream through the RX JESD204B IP core and transport layer, the ADC is configured to output PRBS-9 test data pattern. The ADC is also set to operate with the same configuration as set in the JESD204B IP core. The PRBS checker in the FPGA fabric checks data integrity for one minute.

Figure 5.  Data Integrity Check Using PRBS Checker

This figure shows the conceptual test setup for data integrity checking.



The SignalTap II Logic Analyzer tool monitors the operation of the RX transport layer.

Table 3.   Transport Layer Test Cases

Test Case

Objective

Description

Passing Criteria

TL.1

Check the transport layer mapping using PRBS-9 test pattern.

The following signal in altera_jesd204_transport_rx_top.sv are tapped:

  • jesd204_rx_data_valid

The following signals in jesd204b_ed.v are tapped:

  • data_error
  • jesd204_rx_int

The rxframe_clk is used as the SignalTap II sampling clock.

The data_error signal indicates a pass or fail for the PRBS checker.

  • The jesd204_rx_data_valid signal is asserted.
  • The data_error and jesd204_rx_int signals are deasserted.

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