AN 710: Altera JESD204B MegaCore Function and ADI AD9680 Hardware Checkout Report

ID 683170
Date 5/11/2015
Public

1.3. Hardware Setup for Arria 10 FPGA Development Kit

Figure 3. Hardware Setup

An Arria 10 FPGA Development Kit is used with the ADI AD9680 daughter card module attached to the FMC connector on the development board. 4

  • The FPGA and ADC device clock is supplied by external clock source card through the SMA connectors on the AD9680 EVM.
  • Both the FPGA and ADC device clock must be sourced from the same clock source card with two different frequencies, one for the FPGA and one for ADC.
  • For subclass 1, the FPGA generates SYSREF for the JESD204B IP core as well as the AD9680 device.
Figure 4. System Diagram

The system-level diagram shows how the different modules connect in this design.

In this setup, where LMF=222, the data rate of transceiver lanes is 12.5 Gbps. An external clock source card provides 312.5 MHz clock to the FPGA and 625 MHz sampling clock to AD9680 device.

4 The AD9680 EVM used in this report differs from the production version of AD9680-1000EBZ EVM. However, there is no difference in terms of functionality between these two EVM.

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