3.2. I/O Pins Migration Guidelines
The following table lists the design guidelines for GPIO pins for banks 3A, 3B, 3C, and 3D.
| Pin | I/O Bank | Board Design Guidelines |
|---|---|---|
| GPIO Pin | 3A | The GPIO pins for bank 3A in the HF35 package of the Intel® Stratix® 10 GX400 or SX400 device supports single-ended differential I/O standard at 1.2V, 1.5V, and 1.8V. The mini-LVDS, RSDS, and LVDS I/O standards are supported only in dedicated clock pins, for reference clock purpose only. The pin and its function can be migrated to the HF35 package of the Intel® Stratix® 10 GX650 or SX650 device. If the bank 3A in the HF35 package of the Intel® Stratix® 10 GX650 or SX650 device is used for EMIF or LVDS SERDES in GPIO, then it is not migratable to the HF35 package of the Intel® Stratix® 10 GX400 or SX400 device. Leave these pins as NC. For more information, refer to Figure 3. |
| 3B | The GPIO pins for bank 3B support the same features between the HF35 package of the Intel® Stratix® 10 GX400 or SX400 device and the HF35 package of the Intel® Stratix® 10 GX650 or SX650 device. The design is fully compatible and migratable. | |
| 3C | The bank 3C of the HF35 package of the Intel® Stratix® 10 GX400 or SX400 device supports only 3.0V or 3.3V. Therefore, it is not a direct migration to the HF35 package of the Intel® Stratix® 10 GX650 or SX650 device and vice versa. Leave the GPIO pin as NC when it is not migratable after device migration. Consider to place a 0Ω resistor for the ease to disconnect the connection or remove the interface component. For more information, refer to the Figure 3 . However, if you need to keep the I/O pin in your design after the device migration, you can design it as per Figure 4. Place a level shifter which can level shift to the same voltage level as required by the GPIO pin. By implementing this design, you will be able to migrate those single-ended non-reference voltage I/O to the new target device. |
|
| 3D | The bank 3D of the HF35 package of the Intel® Stratix® 10 GX400 or SX400 device supports only 30 GPIO pins. Please refer to the Table 3 to identify the migratable I/O pins if your design starts with the HF35 package of the Intel® Stratix® 10 GX650 or SX650 device. For the non-migratable pins, leave the pins as NC when your design starts with the HF35 package of the Intel® Stratix® 10 GX650 or SX650 device. For more information, refer to Figure 3. The GPIO pins for bank 3D in the HF35 package of the Intel® Stratix® 10 GX400 or SX400 device supports single-ended and differential I/O standards at 1.2V, 1.5V, and 1.8V. Mini-LVDS, RSDS, and LVDS I/O standards are only supported as a dedicated clock pin for the reference clock purpose only. These pins and their functions can be migrated directly or indirectly to the HF35 package of the Intel® Stratix® 10 GX650 or SX650 device. If the bank 3D in the HF35 package of the Intel® Stratix® 10 GX650 or SX650 device is used for EMIF or LVDS SERDES in GPIO, it is not migratable to the HF35 package of the Intel® Stratix® 10 GX400 or SX400 device. Leave these pins as NC. If you need to migrate the non-reference single-ended I/O from the HF35 package of the Intel® Stratix® 10 GX650 or SX650 device to the HF35 package of the Intel® Stratix® 10 GX400 or SX400 device as compatible pins with different voltage level, you may design the board as shown in Figure 5. |
Figure 3. GPIO Pin for Bank 3A
Figure 4. GPIO Pin for Bank 3C
Figure 5. GPIO Pin for Bank 3D