AN 921: Device Migration Guidelines for Intel® Stratix® 10 HF35 Package

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ID 683163
Date 9/11/2020
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Device Migration Overview 3. Hardware Design Guidelines 4. Intel® Quartus® Prime Software Design Migration 5. Document Revision History for AN921: Device Migration Guidelines for Intel® Stratix® 10 HF35 Package
3. Hardware Design Guidelines x
3.1. Power Pin Migration Guidelines 3.2. I/O Pins Migration Guidelines 3.3. VREF Pin Migration Guidelines 3.4. RZQ Pin Migration Guidelines
4. Intel® Quartus® Prime Software Design Migration x
4.1. Migration via Migration GUI for 1SG040HH2F3512VG-1SG065HH3F3512VG Devices 4.2. Migration Using Migration UI for 1SX065HH3F3512LG-1SX040HH2F3512LG Devices
1. Introduction
2. Device Migration Overview
3. Hardware Design Guidelines
4. Intel® Quartus® Prime Software Design Migration
5. Document Revision History for AN921: Device Migration Guidelines for Intel® Stratix® 10 HF35 Package

3.3. VREF Pin Migration Guidelines

This table describes the design migration guidelines for the VREF pins.

Table 6.   VREF Pin Board Design Guidelines
Pin I/O Bank Board Design Guidelines
VREF Pin 3A The VREF pin is compatible for migration. If VREF pins are not used, connect them either to the VCCIO in the bank where the pins reside or to GND.
3B The VREF pin is compatible for migration. If VREF pins are not used, connect them either to the VCCIO in the bank where the pins reside or to GND.
3C The VREFB3CN0 pin at the HF35 package of the Intel® Stratix® 10 GX400 or SX400 device must always be connected to GND, it is not migratable to the HF35 package of the Intel® Stratix® 10 GX650 or SX650 device.

If the VREF pin in the original board design uses the HF35 package of the Intel® Stratix® 10 GX650 or SX650 device, then you need to connect the pin to GND when migrating to the HF35 package of the Intel® Stratix® 10 GX400 or SX400 device. You may design your board trace design with changeable resistor options as shown in Figure 6.

3D The VCCIO3D pin for the HF35 package of the Intel® Stratix® 10 GX400 or SX400 device only supports 1.8V. The other VCCIO voltage level such as 1.2V and 1.5V are not supported. The VREF power rail must follow the I/O standard used. If VREF pins are not used, then connect them either to the VCCIO in the bank where the pins reside or to GND.
Figure 6.  VREF Pin Bank 3C
Level Two Title