AN 921: Device Migration Guidelines for Intel® Stratix® 10 HF35 Package

ID 683163
Date 9/11/2020
Public

2. Device Migration Overview

You can perform device migration between the HF35 package of the Intel® Stratix® 10 GX 400 and Intel® Stratix® 10 SX 400 to Intel® Stratix® 10 GX 650 and Intel® Stratix® 10 SX 650. You must consider the following device migration guidelines during the early board designing stage to ensure the migration compatibility.
  • Power rail design
    • VCCIO pins for the devices
    • VREFB3[A,B,C,D]N0
  • I/O pin function
    • Pin location and pin function
    • I/O features such as I/O standards and its supported features
  • Intel® Quartus® Prime design
    • Migratable Intel® Quartus® Prime design per I/O pin function availability.

The board design must include the features planned for the target device migration to avoid board re-designing.

The following table provides an overview of the migratable and non-migratable I/O banks. I/O banks 2K, 2L, 2M, 2N, and 3B are fully compatible and you can freely migrate the design to the target device. However, banks 3A and 3D are partially compatible as only selected I/O standard and I/O pin count are supported.

Table 1.  Migratable and Non-Migratable I/O Banks
I/O Bank Migration Condition
2K Fully compatible for all single-ended and differential I/O standard.
2L
2M
2N
3A Partially compatible for single-ended non-voltage reference signals and non-LVDS SERDES differential I/O (LVDS I/O standard works only for a dedicated reference clock pin).
3B Fully compatible for all single-ended and differential I/O standards.
3C Incompatible.
3D Partially compatible for single-ended non-voltage reference signals and non-LVDS SERDES differential I/O (LVDS I/O standard works only for a dedicated reference clock pin). Only 30 I/O pins are available in the HF35 package of the Intel® Stratix® 10 GX 400 and Intel® Stratix® 10 SX 400 devices.

The table below shows the supported I/O standard comparison between the HF35 package of Intel® Stratix® 10 GX 400/ Intel® Stratix® 10 SX 400 and Intel® Stratix® 10 GX 650/ Intel® Stratix® 10 SX650 devices. The supported feature for each I/O standard is available in the Intel® Stratix® 10 General Purpose I/O User Guide.

Table 2.  The I/O Standard Comparison between the HF35 package of Intel® Stratix® 10 GX 400/ Intel® Stratix® 10 SX 400 and Intel® Stratix® 10 GX 650/ Intel® Stratix® 10 SX 650 Devices
Bank Intel® Stratix® 10 GX 400/SX 400 (HF35 Package) Intel® Stratix® 10 GX 650/SX 650 (HF35 Package)
3A Supports 1.2V, 1.5V, and 1.8V single-ended and differential I/O standards, except for the EMIF applications and LVDS SERDES functions. The LVDS I/O standard is supported only in a dedicated reference clock pin for the reference clock function. Supports 1.2V, 1.5V, and 1.8V single-ended and differential I/O standards as stated in the Intel® Stratix® 10 General Purpose I/O User Guide.
3B Supports 1.2V, 1.5V, and 1.8V single-ended and differential I/O standards as stated in the Intel® Stratix® 10 General Purpose I/O User Guide. Supports 1.2V, 1.5V, and 1.8V single-ended and differential I/O standards as stated in the Intel® Stratix® 10 General Purpose I/O User Guide.
3C Supports 3.0V and 3.3V single-ended I/O standard only. Supports 1.2V, 1.5V, and 1.8V single-ended and differential I/O standards as stated in the Intel® Stratix® 10 General Purpose I/O User Guide.
3D Supports 1.8V single-ended I/O and differential I/O standards, except for the EMIF and LVDS functions. The LVDS I/O standard is supported only in a dedicated reference clock pin for the reference clock function. Supports 1.2V, 1.5V, and 1.8V single-ended and differential I/O standards as stated in the Intel® Stratix® 10 General Purpose I/O User Guide.

There are a total of 30 pins in bank 3D of the HF35 package in the Intel® Stratix® 10 GX 400/SX400 which are fanned out to package. The following table shows the pin location comparison for the HF35 package of the Intel® Stratix® 10 GX 400/SX 400 and Intel® Stratix® 10 GX 650/SX 650 devices. You must fully understand the compatibility of the I/O pins for migration before deciding which pin to use in your design.

Table 3.  Pin Location Comparison for the HF35 package of the Intel® Stratix® 10 GX 400/SX 400 and Intel® Stratix® 10 GX 650/SX 650 Devices
Intel Stratix 10 GX 400/SX 400 (HF35 Package) Intel Stratix 10 GX 650/SX 650 (HF35 Package)
Pin Name/Function Pin Location Pin Name/Function Pin Location
IO M5 IO M5
IO M6 IO M6
IO L8 IO L8
IO K7 IO K7
IO M3 IO M3
IO N3 IO N3
IO L7 IO L7
IO M7 IO M7
IO N1 IO N1
IO M1 IO M1
IO H5 IO H5
IO G5 IO G5
IO N5 IO N5
IO N4 IO N4
IO J6 IO J6
IO K5 IO K5
IO P1 IO P1
IO P2 IO P2
IO K6 IO K6
IO L5 IO L5
IO P3 IO P3
IO P4 IO P4
IO H4 IO H4
IO H3 IO H3
IO R1 IO R1
IO R2 IO R2
IO K4 IO K4
IO J4 IO J4
IO R4 IO R4
IO R5 IO R5
VREFB3DN0 M8 VREFB3DN0 M8
NC J1 IO J1
NC H1 IO H1
NC T2 IO T2
NC T3 IO T3
NC L3 IO L3
NC L4 IO L4
NC T4 IO T4
NC T5 IO T5
NC J3 IO J3
NC J2 IO J2
NC U1 IO U1
NC U2 IO U2
NC L2 IO L2
NC M2 IO M2
NC V1 IO V1
NC W1 IO W1
NC K2 IO K2
NC K1 IO K1

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