1. Intel® HLS Compiler Pro Edition Best Practices Guide 2. Best Practices for Coding and Compiling Your Component 3. FPGA Concepts 4. Interface Best Practices 5. Loop Best Practices 6. fMAX Bottleneck Best Practices 7. Memory Architecture Best Practices 8. System of Tasks Best Practices 9. Datatype Best Practices 10. Advanced Troubleshooting A. Intel® HLS Compiler Pro Edition Best Practices Guide Archives B. Document Revision History for Intel® HLS Compiler Pro Edition Best Practices Guide
5.1. Reuse Hardware By Calling It In a Loop 5.2. Parallelize Loops 5.3. Construct Well-Formed Loops 5.4. Minimize Loop-Carried Dependencies 5.5. Avoid Complex Loop-Exit Conditions 5.6. Convert Nested Loops into a Single Loop 5.7. Place if-Statements in the Lowest Possible Scope in a Loop Nest 5.8. Declare Variables in the Deepest Scope Possible 5.9. Raise Loop II to Increase fMAX 5.10. Control Loop Interleaving
184.108.40.206. Task Parallelism
The compiler achieves concurrency by scheduling independent individual operations to execute simultaneously, but it does not achieve concurrency at coarser granularities (for example, across loops).
For larger code structures to execute in parallel with each other, you must write them as separate components or tasks that launch simultaneously. These components or tasks then run independently, and synchronize and communicate using pipes or streams, as shown in the following figure:
Figure 21. Multiple Task Functions Running Asynchronously
For details, see Systems of Tasks in the Intel® High Level Synthesis Compiler Pro Edition Reference Manual .
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