Intel® High Level Synthesis Compiler Pro Edition: Best Practices Guide

ID 683152
Date 12/19/2022

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Document Table of Contents

6. fMAX Bottleneck Best Practices

The fMAX of your component can be limited for various reasons. Review these best practices to understand some common fMAX bottlenecks and how to mitigate them.

Tutorials Demonstrating fMAX Bottleneck Best Practices

The Intel® HLS Compiler Pro Edition comes with a number of tutorials that illustrate important Intel® HLS Compiler concepts and demonstrate good coding practices.

Review the following tutorials to learn about fMAX bottleneck best practices that might apply to your design:
Tutorial Description
You can find these tutorials in the following location on your Intel® Quartus® Prime system:
best_practices/ fpga_reg Demonstrates how manually adding pipeline registers can increase fMAX
best_practices/ overview Demonstrates how fMAX can depend on the interface used in your component.
best_practices/ parallelize_array_operation Demonstrates how to improve fMAX by correcting a bottleneck that arises when performing operations on an array in a loop.
best_practices/ reduce_exit_fifo_width Demonstrates how to improve fMAX by reducing the width of the FIFO belonging to the exit node of a stall-free cluster
best_practices/ relax_reduction_dependency Demonstrates how fMAX can depend on the loop-carried feedback path.