Intel® High Level Synthesis Compiler Pro Edition: Best Practices Guide

ID 683152
Date 12/19/2022

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2. Best Practices for Coding and Compiling Your Component

After you verify the functional correctness of your component, you might want to improve the performance and FPGA area utilization of your component. Learn about the best practices for coding and compiling your component so that you can determine which practices can help you optimize your component.

As you optimize your component, apply the best practices techniques in the following areas, roughly in the order listed. Also, review the example designs and tutorials provided with the Intel® High Level Synthesis (HLS) Compiler to see how some of these techniques can be implemented.

For an example of the full Intel® HLS Compiler design flow, watch the HLS Walkthrough series at the Intel FPGA channel on YouTube or complete the full-design tutorial found in <quartus_installdir>/hls/examples/tutorials/usability.
  • Understand FPGA Concepts

    A key best practice to help you get the most out of the Intel® HLS Compiler is to understand important concepts about FPGAs. With an understanding of FPGA architecture, and some FPGA hardware design concepts and methods, you can create better designs that take advantage of your target FPGA devices.

  • Interface Best Practices

    With the Intel® High Level Synthesis Compiler, your component can have a variety of interfaces: from basic wires to the Avalon Streaming and Avalon Memory-Mapped Host interfaces. Review the interface best practices to help you choose and configure the right interface for your component.

  • Loop Best Practices

    The Intel® High Level Synthesis Compiler pipelines your loops to enhance throughput. Review these loop best practices to learn techniques to optimize your loops to boost the performance of your component.

  • Memory Architecture Best Practices

    The Intel® High Level Synthesis Compiler infers efficient memory architectures (like memory width, number of banks and ports) in a component by adapting the architecture to the memory access patterns of your component. Review the memory architecture best practices to learn how you can get the best memory architecture for your component from the compiler.

  • System of Tasks Best Practices

    Using a system of HLS tasks in your component enables a variety of design structures that you can implement including executing multiple loops in parallel and sharing an expensive compute block.

  • Datatype Best Practices

    The datatypes in your component and possible conversions or casting that they might undergo can significantly affect the performance and FPGA area usage of your component. Review the datatype best practices for tips and guidance how best to control datatype sizes and conversions in your component.

  • Alternative Algorithms

    The Intel® High Level Synthesis Compiler lets you compile a component quickly to get initial insights into the performance and area utilization of your component. Take advantage of this speed to try larger algorithm changes to see how those changes affect your component performance.