Visible to Intel only — GUID: jgj1593102533539
Ixiasoft
Visible to Intel only — GUID: jgj1593102533539
Ixiasoft
3.1.1.2. Register
A register is the most basic storage element in an FPGA. It has an input (in), an output (out), and a clock signal (clk). It is synchronous, that is, it synchronizes output changes to a clock. In an ALM, a register may store the output of the LUT.
The following figure illustrates a register:
The following figure illustrates the waveform of register signals:
The input data propagates to the output on every clock cycle. The output remains unchanged between clock cycles.
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