Intel® High Level Synthesis Compiler Pro Edition: Best Practices Guide

ID 683152
Date 12/13/2021

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Document Table of Contents Handshaking Between Clusters

By default, the handshaking protocol between clusters is a simple stall/valid protocol. Data from the upstream cluster is consumed when the stall signal is low and the valid signal is high.

Figure 8. Handshaking Between Clusters

Hyper-Optimized Handshaking

If the distance across the FPGA between these two clusters is large, handshaking may become the critical path that affects peak fMAX. in the design

To improve these cases, the Intel® HLS Compiler can add pipelining registers to the stall/valid protocol to ease the critical path and improve fMAX. This enhanced handshaking protocol is called hyper-optimized handshaking.

Figure 9. Hyper-Optimized Handshaking Data Flow

The following timing diagram illustrates an example of upstream cluster 1 and downstream cluster 2 with two pipelining registers inserted in-between:

Figure 10. Hyper-Optimized Handshaking

Restriction: Hyper-optimized handshaking is currently available only for the Intel® Agilex™ and Intel® Stratix® 10 device families.