Intel® High Level Synthesis Compiler Pro Edition: Best Practices Guide

ID 683152
Date 12/13/2021
Public

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3.1.1.2. Register

A register is the most basic storage element in an FPGA. It has an input (in), an output (out), and a clock signal (clk). It is synchronous, that is, it synchronizes output changes to a clock. In an ALM, a register may store the output of the LUT.

The following figure illustrates a register:



Note: The clock signal is implied and not shown in some figures.

The following figure illustrates the waveform of register signals:



The input data propagates to the output on every clock cycle. The output remains unchanged between clock cycles.

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