Intel® High Level Synthesis Compiler Pro Edition: Best Practices Guide

ID 683152
Date 12/13/2021
Public

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Document Table of Contents

B. Document Revision History for Intel® HLS Compiler Pro Edition Best Practices Guide

Document Version Intel® HLS Compiler Pro Edition Version Changes
2021.12.13 21.4
2021.10.04 21.3
  • Maintenance release.
2021.06.21 21.2
  • Revised references to Avalon Interfaces to align with new Avalon Interconnect terminology. Avalon master interfaces are now Avalon host interfaces, and Avalon slave interfaces are now Avalon agent interfaces.
2021.03.29 21.1
2020.12.14 20.4
2020.09.28 20.3
2020.06.22 20.2
2020.04.13 20.1
2020.01.27 19.4
2019.12.16 19.4
  • Removed information about Intel® HLS Compiler Standard Edition.

    For best practices information for the Intel® HLS Compiler Standard Edition, see Intel® HLS Compiler Standard Edition Best Practices Guide .

  • Added information to Example: Specifying Bank-Selection Bits for Local Memory Addresses to explain the difference between the element-address bank-selection bits selected with the hls_bankbits attribute and the byte- address bank-selection bits reported in the Function Memory Viewer in the High-Level Design Reports.
  • References to the Component Viewer have been replaced with references to the Function View of the Graph Viewer.
  • Reference to the Component Memory Viewer have been replaced with references to the Function Memory Viewer.

Document Revision History for Intel® HLS Compiler Best Practices Guide

Previous versions of the Intel® HLS Compiler Best Practices Guide contained information for both Intel® HLS Compiler Standard Edition and Intel® HLS Compiler Pro Edition.

Document Version Intel® Quartus® Prime Version Changes
2019.09.30 19.3
2019.07.01 19.2
  • Maintenance release.
2019.04.01 19.1
2018.12.24 18.1
  • Updated to Loop Best Practices to include information about function inlining in components and using loops to minimize the resulting hardware duplication.
2018.09.24 18.1
2018.07.02 18.0
  • Added a new chapter, Advanced Troubleshooting, to help you troubleshoot when your component behaves differently in simulation and emulation, and when your component has unexpectedly poor performance, resource utilization, or both.
2018.05.07 18.0
  • Starting with Intel® Quartus® Prime Version 18.0, the features and devices supported by the Intel® HLS Compiler depend on what edition of Intel® Quartus® Prime you have. Intel® HLS Compiler publications now use icons to indicate content and features that apply only to a specific edition as follows:
    Indicates that a feature or content applies only to the Intel® HLS Compiler provided with Intel® Quartus® Prime Pro Edition.
    Indicates that a feature or content applies only to the Intel® HLS Compiler provided with Intel® Quartus® Prime Standard Edition.
  • Added best_practices/loop_coalesce to the list of tutorials in Loop Best Practices.
  • Added interfaces/explicit_streams_packets_ready_empty to list of tutorials in Interface Best Practices.
  • Revised Example: Specifying Bank-Selection Bits for Local Memory Addresses with improved descriptions and new graphics that reflect what you would see in the high-level design reports (report.html) for the example component.
  • Updated Example: Overriding a Coalesced Memory Architecture with new images to show the memory structures as well as how the FPGA resource usage differs between the two components
2017.12.22 17.1.1
2017.11.06 17.1 Initial release.

Parts of this book consist of content previously found in the Intel® High Level Synthesis Compiler User Guide and the Intel® High Level Synthesis Compiler Reference Manual.

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