Intel® High Level Synthesis Compiler Pro Edition: Reference Manual

ID 683349
Date 12/13/2021
Public

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6.1. Loop Initiation Interval (ii Pragma)

The initiation interval, or II, is the number of clock cycles between the launch of successive loop iterations. Use the ii pragma to direct the Intel® High Level Synthesis (HLS) Compiler to attempt to set the initiation interval (II) for the loop that follows the pragma declaration. If the compiler cannot achieve the specified II for the loop, then the compilation errors out.
You might want to increase the II of a loop to get an fMAX improvement in your component. A loop is a good candidate to have the ii pragma applied to increase its loop II if the loop meets any of the following conditions:
  • The loop is not critical to the throughput of your component.
  • The running time of the loop is small compared to other loops it might contain.

You can also apply the ii pragma to force a loop to an II of 1 and accept a possible fMAX penalty.

To specify a loop initiation interval for a loop, specify the pragma before the loop as follows:
#pragma ii <desired_initiation_interval>
The <desired_initiation_interval> parameter is required and is an integer that specifies the number of clock cycles to wait between the beginning of execution of successive loop iterations.

You can also direct the compiler to attempt to achieve an II for your component with the hls_component_ii (<N>) component attribute. For more information, refer to hls_component_ii .

To learn more about the effects of applying the ii loop pragma, review the following tutorial:
<quartus_installdir>/hls/examples/tutorials/best_practices/set_target_fmax_1

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