Intel® High Level Synthesis Compiler Pro Edition: Best Practices Guide

ID 683152
Date 12/13/2021

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Document Table of Contents Dynamic Scheduling

The Intel® HLS Compiler generates pipelined datapaths that are dynamically scheduled.

A dynamically scheduled portion of the datapath does not pass data to its successor until its successor signals that it is ready to receive it.

This signaling is accomplished using handshaking control logic. For example, a variable latency load from memory may refuse to accept its predecessors' data until the load is complete.

Handshaking helps remove bubbles in the pipeline, which increases occupancy. For more information about bubbles, refer to Occupancy.

The following figure illustrates four regions of dynamically scheduled logic:

Figure 4. Dynamically Scheduled LogicBlack arrows represent data and valid signals and red arrows represent signals to stall incoming valid data flow.