F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 1/26/2024

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Document Table of Contents

3.3.4. Tag Allocation

The F-Tile PCIe Hard IP supports the 10-bit tag Requester capability in the x16 Controller (Port 0) only. It supports up to 512 outstanding Non-Posted Requests (NPRs) with valid tag values ranging from 256 to 767.

By default, the x16 (Port0) controller supports 10-bit tag Requester capability. The x8 (Port 1) and x4 Controllers (Port 2/3) don’t support the 10-bit tag Requester capability, although they support the 10-bit Completer capability. Both x8 and x4 Controllers can allow up to 256 outstanding NPRs with valid tag values ranging from 0 to 255 .

When enabling both 10-bit tags and 8-bit tags, the LSB 8 bits of the 8-bit tags cannot be shared with the LSB 8 bits of the 10-bit tags. For example, if you want to use 64 tags as 8-bit tags and the rest of the tags as 10-bit tags, you can partition the tag space as follows:
  • 8-bit tags : 0 - 63
  • 10-bit tags : 320 - 511, 576 - 767
Note: All PFs and their associated VFs share the same tag space. This means that different PFs and VFs cannot have outstanding tags having the same tag values.