F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 1/26/2024

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

6.2.6. Analog Options

Figure 68. Analog Parameters Tab
Table 109.  Analog Parameters
Parameter Value Default Value Description
Enable PCIe low loss Disable/Enable Enable

When you select Enable, you enable the transceiver analog settings for low loss PCIe design.

Note: This parameter should only be enabled for chip-to-chip design where the insertion loss from endpoint silicon pad to root port silicon pad including the package insertion loss is below 8 dB at 8GHz.