F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 1/26/2024

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7.7. PIPE Mode Simulation

The PIPE Simulation Mode exposes extra signal ports in the F-Tile AVST IP for simulation purposes only.

Note: FASTSIM mode is not supported for PIPE simulation mode.
You must implement the following steps to enable the simulation mode.
  1. Connect the PIPE signal ports such as o_txpipe[n]_* and i_rxpipe[n]_* to the ports of Verification IP (VIP).
  2. Connect to pin_perst of F-Tile AVST IP from VIP reset signal.
  3. Connect o_p1__prot_f2t_ssr to VIP to generate the PIPE reset to VIP according to the selected topology. Please refer to section 7.7.2 for more details.
  4. Connect the PIPE clock signals i_pclk_x* to VIP and ensure these signals are driven according to PCIe speed rate. Please refer to section 7.7.1 for more details.
  5. Run the Logic Generation Flow to apply the connections.
  6. Add compile option +define+gdrb_GDR_PCIE_SS_DV to the simulation script. Example is shown below.