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1. SDI II IP Core Quick Reference
2. SDI II IP Core Overview
3. SDI II IP Core Getting Started
4. SDI II IP Core Parameters
5. SDI II IP Core Functional Description
6. SDI II IP Core Signals
7. SDI II IP Core Design Considerations
8. SDI II IP Core Testbench and Design Examples
9. SDI II Intel® FPGA IP User Guide Archives
10. Document Revision History for the SDI II Intel® FPGA IP User Guide
5.3.1. Insert Line
5.3.2. Insert/Check CRC
5.3.3. Insert Payload ID
5.3.4. Match TRS
5.3.5. Scrambler
5.3.6. TX Sample
5.3.7. Clock Enable Generator
5.3.8. RX Sample
5.3.9. Detect Video Standard
5.3.10. Detect 1 and 1/1.001 Rates
5.3.11. Transceiver Controller
5.3.12. Descrambler
5.3.13. TRS Aligner
5.3.14. 3Gb Demux
5.3.15. Extract Line
5.3.16. Extract Payload ID
5.3.17. Detect Format
5.3.18. Sync Streams
5.3.19. Convert SD Bits
5.3.20. Insert Sync Bits
5.3.21. Remove Sync Bits
5.4.1. HD-SDI Dual Link to 3G-SDI (Level B) Conversion
5.4.2. 3G-SDI (Level B) to HD-SDI Dual Link Conversion
5.4.3. SMPTE RP168 Switching Support
5.4.4. SD 20-Bit Interface for Dual/Triple Rate
5.4.5. Dynamic TX Clock Switching for Arria V, Cyclone V, and Stratix V Devices
5.4.6. Intel FPGA Video Streaming Interface
7.1.2.1. Changing RX CDR Reference Clock in Transceiver Native PHY IP Core
7.1.2.2. Merging Simplex Mode Transceiver in the Same Channel
7.1.2.3. Using Generated Reconfiguration Management for Triple and Multi Rates
7.1.2.4. Ensuring Independent RX and TX Operations in the Same Channel
7.1.2.5. Potential Routing Problem During Fitter Stage in Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
7.1.2.6. Unconstrained Clocks in SDI Multi-Rate RX Using Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
7.1.2.7. Unused Transceiver Channels
7.1.2.8. Routing Transceiver Reference Clock Pins to Core Logic in Intel® Stratix® 10 Devices
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5.2. Transceiver
The transceiver block consists of two components:
- PHY management and adapter
- Native PHY IP
Note: The transceiver block is only available for Arria V, Cyclone V, and Stratix V devices. For Intel® Arria® 10, Intel® Cyclone® 10 GX, Intel® Stratix® 10 and Intel Agilex® 7 F-Tile devices, you must generate the transceiver and/or the TX PLL instances separately; refer to SDI Presets in the Transceiver Native PHY Intel Arria 10/Cyclone 10 FPGA IP and L-Tile/H-Tile Transceiver Native PHY Intel Stratix 10 IP Cores.
For Arria V, Cyclone V, and Stratix V devices, the SDI II IP core instantiates the Native PHY IP core using the Tcl file associated with each device.
The block diagram below illustrates the Native PHY IP core setup in the SDI II IP core (duplex) data path.
Figure 19. Native PHY IP Core Setup in Duplex ModeThe Native PHY IP core does not include an embedded reset controller and an Avalon® Memory-Mapped (Avalon-MM) interface. This PHY IP core exposes all signals directly as ports. To implement reset functionality for a new IP core, the transceiver reset controller is required to handle all the transceiver reset sequencing. The transceiver reset controller controls the embedded reset controller and also manages additional control options such as automatic or manual reset recovery mode.
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