SDI II Intel® FPGA IP User Guide

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ID 683133
Date 4/03/2023
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Document Table of Contents
Document Table of Contents x
1. SDI II IP Core Quick Reference 2. SDI II IP Core Overview 3. SDI II IP Core Getting Started 4. SDI II IP Core Parameters 5. SDI II IP Core Functional Description 6. SDI II IP Core Signals 7. SDI II IP Core Design Considerations 8. SDI II IP Core Testbench and Design Examples 9. SDI II Intel® FPGA IP User Guide Archives 10. Document Revision History for the SDI II Intel® FPGA IP User Guide
2. SDI II IP Core Overview x
2.1. Release Information 2.2. Device Family Support 2.3. General Description 2.4. Performance and Resource Utilization
3. SDI II IP Core Getting Started x
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. Design Walkthrough 3.3. SDI II IP Core Component Files 3.4. Compiling the SDI II IP Core Design 3.5. Programming an FPGA
3.1. Installing and Licensing Intel® FPGA IP Cores x
3.1.1. Intel® FPGA IP Evaluation Mode
3.2. Design Walkthrough x
3.2.1. Creating a New Intel® Quartus® Prime Project 3.2.2. Launching IP Catalog 3.2.3. Parameterizing the IP Core 3.2.4. Generating a Design Example and Simulation Testbench
5. SDI II IP Core Functional Description x
5.1. Protocol 5.2. Transceiver 5.3. Submodules 5.4. Optional Features
5.1. Protocol x
5.1.1. Transmitter 5.1.2. Receiver
5.3. Submodules x
5.3.1. Insert Line 5.3.2. Insert/Check CRC 5.3.3. Insert Payload ID 5.3.4. Match TRS 5.3.5. Scrambler 5.3.6. TX Sample 5.3.7. Clock Enable Generator 5.3.8. RX Sample 5.3.9. Detect Video Standard 5.3.10. Detect 1 and 1/1.001 Rates 5.3.11. Transceiver Controller 5.3.12. Descrambler 5.3.13. TRS Aligner 5.3.14. 3Gb Demux 5.3.15. Extract Line 5.3.16. Extract Payload ID 5.3.17. Detect Format 5.3.18. Sync Streams 5.3.19. Convert SD Bits 5.3.20. Insert Sync Bits 5.3.21. Remove Sync Bits
5.4. Optional Features x
5.4.1. HD-SDI Dual Link to 3G-SDI (Level B) Conversion 5.4.2. 3G-SDI (Level B) to HD-SDI Dual Link Conversion 5.4.3. SMPTE RP168 Switching Support 5.4.4. SD 20-Bit Interface for Dual/Triple Rate 5.4.5. Dynamic TX Clock Switching for Arria V, Cyclone V, and Stratix V Devices 5.4.6. Intel FPGA Video Streaming Interface
5.4.6. Intel FPGA Video Streaming Interface x
5.4.6.1. RGB Pixel Packing 5.4.6.2. YCbCr 444 Pixel Packing 5.4.6.3. YCbCr 422 Pixel Packing 5.4.6.4. Supported Modes
6. SDI II IP Core Signals x
6.1. SDI II IP Core Resets and Clocks 6.2. Transmitter Protocol Signals 6.3. Receiver Protocol Signals 6.4. Transceiver Signals 6.5. Transmitter Streaming Video and Control Signals 6.6. Receiver Streaming Video and Control Signals
6.2. Transmitter Protocol Signals x
6.2.1. Image Mapping
6.3. Receiver Protocol Signals x
6.3.1. rx_format
7. SDI II IP Core Design Considerations x
7.1. Transceiver Handling Guidelines 7.2. Timing Violation 7.3. SDI II IP Core Registers
7.1. Transceiver Handling Guidelines x
7.1.1. Handling Transceiver in Arria V, Cyclone V, and Stratix V Devices 7.1.2. Handling Transceiver in Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 Devices 7.1.3. Handling Transceiver in Intel Agilex® 7 F-Tile Devices
7.1.1. Handling Transceiver in Arria V, Cyclone V, and Stratix V Devices x
7.1.1.1. Modifying the Transceiver Reconfiguration Controller 7.1.1.2. Modifying the Reconfiguration Management 7.1.1.3. Modifying the Reconfiguration Router
7.1.2. Handling Transceiver in Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 Devices x
7.1.2.1. Changing RX CDR Reference Clock in Transceiver Native PHY IP Core 7.1.2.2. Merging Simplex Mode Transceiver in the Same Channel 7.1.2.3. Using Generated Reconfiguration Management for Triple and Multi Rates 7.1.2.4. Ensuring Independent RX and TX Operations in the Same Channel 7.1.2.5. Potential Routing Problem During Fitter Stage in Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices 7.1.2.6. Unconstrained Clocks in SDI Multi-Rate RX Using Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices 7.1.2.7. Unused Transceiver Channels 7.1.2.8. Routing Transceiver Reference Clock Pins to Core Logic in Intel® Stratix® 10 Devices
7.1.3. Handling Transceiver in Intel Agilex® 7 F-Tile Devices x
7.1.3.1. System PLL Clocking Mode 7.1.3.2. RX Transceiver Settings 7.1.3.3. TX Transceiver Settings 7.1.3.4. Unused Transceiver Tiles 7.1.3.5. Dynamic Reconfiguration 7.1.3.6. SD-SDI Timing Jitter With External VCXO Which Receive FVH Sync Signals
7.1.3.2. RX Transceiver Settings x
7.1.3.2.1. Multi-rate Designs 7.1.3.2.2. Triple-rate Designs 7.1.3.2.3. Single-rate Designs
7.3. SDI II IP Core Registers x
7.3.1. SDI II Tx Register Summary 7.3.2. SDI II Tx Register Description 7.3.3. SDI II Rx Register Summary 7.3.4. SDI II Rx Register Description
8. SDI II IP Core Testbench and Design Examples x
8.1. Design Examples for Intel® Arria® 10, Intel® Cyclone® 10 GX, Intel® Stratix® 10, and Intel Agilex® 7 F-Tile Devices 8.2. Design Examples for Arria V, Cyclone V, and Stratix V Devices
8.1. Design Examples for Intel® Arria® 10, Intel® Cyclone® 10 GX, Intel® Stratix® 10, and Intel Agilex® 7 F-Tile Devices x
8.1.1. Design Example Presets
8.2. Design Examples for Arria V, Cyclone V, and Stratix V Devices x
8.2.1. Design Example Components 8.2.2. Design Reference 8.2.3. Simulating the SDI II IP Core Design
8.2.1. Design Example Components x
8.2.1.1. Video Pattern Generator 8.2.1.2. Transceiver Reconfiguration Controller 8.2.1.3. Reconfiguration Management 8.2.1.4. Reconfiguration Router 8.2.1.5. Avalon-MM Translators
8.2.2. Design Reference x
8.2.2.1. Video Pattern Generator Signals 8.2.2.2. Transceiver Reconfiguration Controller Signals 8.2.2.3. Reconfiguration Management Parameters 8.2.2.4. Reconfiguration Router Signals
8.2.3. Simulating the SDI II IP Core Design x
8.2.3.1. Simulation Run Time
1. SDI II IP Core Quick Reference
2. SDI II IP Core Overview
3. SDI II IP Core Getting Started
4. SDI II IP Core Parameters
5. SDI II IP Core Functional Description
6. SDI II IP Core Signals
7. SDI II IP Core Design Considerations
8. SDI II IP Core Testbench and Design Examples
9. SDI II Intel® FPGA IP User Guide Archives
10. Document Revision History for the SDI II Intel® FPGA IP User Guide

6.4. Transceiver Signals

Table 24.  Transceiver Serial Data Pins (for Arria V, Cyclone V, and Stratix V Devices)
Signal Direction Description
sdi_tx

Output

Transmitter serial out.
sdi_tx_b

Output

Transmitter serial out for link B.

Note: Applicable for HD-SDI dual link configuration only.
sdi_rx

Input

Receiver serial in.
sdi_rx_b

Input

Receiver serial in for link B.

Note: Applicable for HD-SDI dual link configuration only.
Table 25.  Transceiver Signals
Signal Width Clock Domain Direction Description
xcvr_refclk_sel

1

tx_coreclk

Input

Transceiver reference clock select signal that selects which clock to be used.

  • 0 = xcvr_refclk
  • 1 = xcvr_refclk_alt

Applicable only when you enable the Tx PLL Dynamic Switching option.

Note: Not applicable for Intel® Arria® 10, Intel® Cyclone® 10 GX, Intel® Stratix® 10, and Intel Agilex® 7 F-Tile devices.
tx_pll_locked

1

–

Output

PLL locked signal (TX PLL0) for the Native PHY IP core.

Note: Not applicable for Intel® Arria® 10, Intel® Cyclone® 10 GX, Intel® Stratix® 10, and Intel Agilex® 7 F-Tile devices.
tx_pll_locked_alt

1

–

Output

PLL locked signal (TX PLL1) for the Native PHY IP core.

Applicable only when you enable the Tx PLL Dynamic Switching option.

Note: Not applicable for Intel® Arria® 10, Intel® Cyclone® 10 GX, Intel® Stratix® 10, and Intel Agilex® 7 F-Tile devices.
reconfig_to_xcvr

70N

–

Input

Dynamic reconfiguration input for the Native PHY IP core, where N is the reconfiguration interface.

  • N = 1 for receiver
  • N = 2 for transmitter and bidirectional
Note: Not applicable for Intel® Arria® 10, Intel® Cyclone® 10 GX, Intel® Stratix® 10, and Intel Agilex® 7 F-Tile devices.
reconfig_to_xcvr_b

70N

–

Input

Dynamic reconfiguration input for the Native PHY IP core, where N is the reconfiguration interface.

  • N = 1 for receiver
  • N = 2 for transmitter and bidirectional
Note: For HD-SDI dual link configuration only. Not applicable for Intel Agilex® 7 F-Tile, Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 devices.
reconfig_from_xcvr

46N

–

Output

Dynamic reconfiguration output for the Native PHY IP core, where N is the reconfiguration interface.

  • N = 1 for receiver
  • N = 2 for transmitter and bidirectional
Note: Not applicable for Intel Agilex® 7 F-Tile, Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 devices.
reconfig_from_xcvr_b

46N

–

Output

Dynamic reconfiguration output for the Native PHY IP core, where N is the reconfiguration interface.

  • N = 1 for receiver
  • N = 2 for transmitter and bidirectional
Note: For HD-SDI dual link configuration only. Not applicable for Intel Agilex® 7 F-Tile, Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 devices.
rx_sdi_start_reconfig

1

rx_coreclk

Output

Request to start dynamic reconfiguration. This signal stays asserted until rx_sdi_reconfig_done indicates that the reconfiguration process is complete.

Note: Applicable for dual rate, triple-rate, and multi-rate modes only.
rx_sdi_reconfig_done

1

–

Input

Indicates that dynamic reconfiguration has completed.

This signal should connect to the reconfiguration status signal of the external transceiver reconfiguration management.
  • For Intel Agilex® 7 F-Tile, Arria V, Cyclone V, and Stratix V devices, assertion of this signal indicates to the receiver that the process is done.
  • For Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 devices, deassertion of this signal indicates to the receiver that the process is done.
Note: Applicable for dual rate, triple-rate, and multi-rate modes only.
rx_ready

1

–

Input

Status signal from the transceiver reset controller to indicate when Rx PHY sequence is complete.

Note: Applicable only for Intel® Arria® 10, Intel® Cyclone® 10 GX, Intel® Stratix® 10, and Intel Agilex® 7 F-Tile devices.
gxb_ltr

1

rx_coreclk

Output

Control signal to the transceiver rx_set_locktoref input signal.

Assertion of this signal programs the Rx CDR to lock manually to reference mode.

Note: Applicable only for Intel® Arria® 10, Intel® Cyclone® 10 GX, Intel® Stratix® 10, and Intel Agilex® 7 F-Tile devices.
gxb_ltd

1

rx_coreclk

Output

Control signal to the transceiver rx_set_locktodata input signal.

Note: Applicable only for Intel® Arria® 10, Intel® Cyclone® 10 GX, Intel® Stratix® 10, and Intel Agilex® 7 F-Tile devices.
rx_ready_b 1 -

Input

Status signal from Transceiver Reset Controller to indicate when Rx PHY reset sequence is complete for link B

For HD-SDI dual link receiver protocol configuration only. (Not supported anymore on A10 from 16.1 onwards).
gxb_ltr_b 1 rx_coreclk

Output

Control signal to transceiver rx_set_locktoref input port. When asserted, programs the RX CDR to manual lock to reference mode.

For HD-SDI dual link receiver protocol configuration only. (Not supported anymore on A10 from 16.1 onwards).
gxb_ltd_b 1 rx_coreclk

Output

Control signal to transceiver rx_set_locktodata input port. When asserted, programs the RX CDR to manual lock to data mode.

For HD-SDI dual link receiver protocol configuration only. (Not supported anymore on A10 from 16.1 onwards).
rx_xcvr_reset_ack

1

-

Input

Status signal from transceiver indicating that the Rx transceiver is fully in reset
Level Two Title