SDI II Intel® FPGA IP User Guide

ID 683133
Date 4/03/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

7.3.4. SDI II Rx Register Description

Table 55.  STATUS (0x50)
Name Bit(s) Access Description Reset
Reserved 31:12 - - -
Video locked 11 RO When asserted, indicates current signal value of the SDI frame locked signal. 0x0
Resolution valid 10 RO When asserted, indicates a valid resolution in the sample and line count registers. 0x0
Reserved 9 - - -
Stable 8 RO When asserted, the input video stream has had a consistent line length for two of the last three lines. 0x0
Interlaced 7 RO When asserted, the input video stream is interlaced. Otherwise, the input video stream is progressive. 0x0
Reserved 6:1 - - -
Status 0 RO This bit is asserted when the core is producing data 0x0
Table 56.  ACTIVE_SAMPLE_COUNT (0x52)
Name Bit(s) Access Description Reset
Reserved 31:16 - - -
Active sample count 15:0 RO The detected sample count of the video stream excluding blanking 0x0
Table 57.  F0_ACTIVE_LINE_COUNT (0x53)
Name Bit(s) Access Description Reset
Reserved 31:16 - - -
F0 active line count 15:0 RO The detected line count of the interlaced video field 0 or progressive video excluding blanking. 0x0
Table 58.  F1_ACTIVE_LINE_COUNT (0x54)
Name Bit(s) Access Description Reset
Reserved 31:16 - - -
F1 active line count 15:0 RO The detected line count of the interlaced video field 1 excluding blanking. 0x0
Table 59.  VIDEO_MODE_STANDARD (0x58)
Name Bit(s) Access Description Reset
Reserved 31:4 - - -
SDI mode 3 RO

This bit indicates the received video payload byte 1 bit 0 or the SDI mode for 6G-SDI and 12G-SDI.

0x1: 2081-10-2018 6G-SDI mode 2 and mode 3,

2082-10-2018 12G-SDI mode 2.

0x0: 2081-10-2018 6G-SDI mode 1,

2082-10-2018 12G-SDI mode 1
0x0
SDI video standard 2:0 RO

The detected SDI video standard

0x0: SD-SDI

0x1: HD-SDI

0x2: 3G-SDI Level B

0x3: 3G-SDI Level A

0x4: 6G-SDI Level B

0x5: 6G-SDI Level A

0x7: 12G-SDI Level A
0x0
Table 60.  COLOR_PATTERN (0x5C)
Name Bit(s) Access Description Reset
Reserved 31:13 - - -
Bit Depth 12:10 RO

The detected bit depth of each color sample.

3’d2: 10 bits

3’d4: 12 bits

 
Reserved 9 - - -
Chroma sub-sampling 8:7 RO

The detected chroma sub-sampling.

2’d0: 420

2’d2: 422

2’d3: 444

0x0
Reserved 6:1 - - -
Color space 0 RO

The detected color space.

1’d0: RGB

1’d1: YCbCr

0x0
Table 61.  VPID_BYTE1 (0x5D)
Name Bit(s) Access Description Reset
Reserved 31:8 - - -
SDI video payload ID byte 1 7:0 RW The detected video payload byte 1. 0x0
Table 62.  VPID_BYTE2 (0x5E)
Name Bit(s) Access Description Reset
Reserved 31:8 - - -
SDI video payload ID byte 2 7:0 RW The detected video payload byte 2. 0x0
Table 63.  VPID_BYTE3 (0x5F)
Name Bit(s) Access Description Reset
Reserved 31:8 - - -
SDI video payload ID byte 3 7:0 RW The detected video payload byte 3. 0x0
Table 64.  VPID_BYTE4 (0x60)
Name Bit(s) Access Description Reset
Reserved 31:8 - - -
SDI video payload ID byte 4 7:0 RW The detected video payload byte 4. 0x0
Table 65.  CONTROL (0x64)
Name Bit(s) Access Description Reset
Reserved 31:1 - - -
Go 0 WO Setting this bit to 1 causes the SDI II Rx core to start data output on the next video frame boundary. 0x0