SDI II Intel® FPGA IP User Guide

Download PDF
ID 683133
Date 4/03/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. SDI II IP Core Quick Reference 2. SDI II IP Core Overview 3. SDI II IP Core Getting Started 4. SDI II IP Core Parameters 5. SDI II IP Core Functional Description 6. SDI II IP Core Signals 7. SDI II IP Core Design Considerations 8. SDI II IP Core Testbench and Design Examples 9. SDI II Intel® FPGA IP User Guide Archives 10. Document Revision History for the SDI II Intel® FPGA IP User Guide
2. SDI II IP Core Overview x
2.1. Release Information 2.2. Device Family Support 2.3. General Description 2.4. Performance and Resource Utilization
3. SDI II IP Core Getting Started x
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. Design Walkthrough 3.3. SDI II IP Core Component Files 3.4. Compiling the SDI II IP Core Design 3.5. Programming an FPGA
3.1. Installing and Licensing Intel® FPGA IP Cores x
3.1.1. Intel® FPGA IP Evaluation Mode
3.2. Design Walkthrough x
3.2.1. Creating a New Intel® Quartus® Prime Project 3.2.2. Launching IP Catalog 3.2.3. Parameterizing the IP Core 3.2.4. Generating a Design Example and Simulation Testbench
5. SDI II IP Core Functional Description x
5.1. Protocol 5.2. Transceiver 5.3. Submodules 5.4. Optional Features
5.1. Protocol x
5.1.1. Transmitter 5.1.2. Receiver
5.3. Submodules x
5.3.1. Insert Line 5.3.2. Insert/Check CRC 5.3.3. Insert Payload ID 5.3.4. Match TRS 5.3.5. Scrambler 5.3.6. TX Sample 5.3.7. Clock Enable Generator 5.3.8. RX Sample 5.3.9. Detect Video Standard 5.3.10. Detect 1 and 1/1.001 Rates 5.3.11. Transceiver Controller 5.3.12. Descrambler 5.3.13. TRS Aligner 5.3.14. 3Gb Demux 5.3.15. Extract Line 5.3.16. Extract Payload ID 5.3.17. Detect Format 5.3.18. Sync Streams 5.3.19. Convert SD Bits 5.3.20. Insert Sync Bits 5.3.21. Remove Sync Bits
5.4. Optional Features x
5.4.1. HD-SDI Dual Link to 3G-SDI (Level B) Conversion 5.4.2. 3G-SDI (Level B) to HD-SDI Dual Link Conversion 5.4.3. SMPTE RP168 Switching Support 5.4.4. SD 20-Bit Interface for Dual/Triple Rate 5.4.5. Dynamic TX Clock Switching for Arria V, Cyclone V, and Stratix V Devices 5.4.6. Intel FPGA Video Streaming Interface
5.4.6. Intel FPGA Video Streaming Interface x
5.4.6.1. RGB Pixel Packing 5.4.6.2. YCbCr 444 Pixel Packing 5.4.6.3. YCbCr 422 Pixel Packing 5.4.6.4. Supported Modes
6. SDI II IP Core Signals x
6.1. SDI II IP Core Resets and Clocks 6.2. Transmitter Protocol Signals 6.3. Receiver Protocol Signals 6.4. Transceiver Signals 6.5. Transmitter Streaming Video and Control Signals 6.6. Receiver Streaming Video and Control Signals
6.2. Transmitter Protocol Signals x
6.2.1. Image Mapping
6.3. Receiver Protocol Signals x
6.3.1. rx_format
7. SDI II IP Core Design Considerations x
7.1. Transceiver Handling Guidelines 7.2. Timing Violation 7.3. SDI II IP Core Registers
7.1. Transceiver Handling Guidelines x
7.1.1. Handling Transceiver in Arria V, Cyclone V, and Stratix V Devices 7.1.2. Handling Transceiver in Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 Devices 7.1.3. Handling Transceiver in Intel Agilex® 7 F-Tile Devices
7.1.1. Handling Transceiver in Arria V, Cyclone V, and Stratix V Devices x
7.1.1.1. Modifying the Transceiver Reconfiguration Controller 7.1.1.2. Modifying the Reconfiguration Management 7.1.1.3. Modifying the Reconfiguration Router
7.1.2. Handling Transceiver in Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 Devices x
7.1.2.1. Changing RX CDR Reference Clock in Transceiver Native PHY IP Core 7.1.2.2. Merging Simplex Mode Transceiver in the Same Channel 7.1.2.3. Using Generated Reconfiguration Management for Triple and Multi Rates 7.1.2.4. Ensuring Independent RX and TX Operations in the Same Channel 7.1.2.5. Potential Routing Problem During Fitter Stage in Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices 7.1.2.6. Unconstrained Clocks in SDI Multi-Rate RX Using Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices 7.1.2.7. Unused Transceiver Channels 7.1.2.8. Routing Transceiver Reference Clock Pins to Core Logic in Intel® Stratix® 10 Devices
7.1.3. Handling Transceiver in Intel Agilex® 7 F-Tile Devices x
7.1.3.1. System PLL Clocking Mode 7.1.3.2. RX Transceiver Settings 7.1.3.3. TX Transceiver Settings 7.1.3.4. Unused Transceiver Tiles 7.1.3.5. Dynamic Reconfiguration 7.1.3.6. SD-SDI Timing Jitter With External VCXO Which Receive FVH Sync Signals
7.1.3.2. RX Transceiver Settings x
7.1.3.2.1. Multi-rate Designs 7.1.3.2.2. Triple-rate Designs 7.1.3.2.3. Single-rate Designs
7.3. SDI II IP Core Registers x
7.3.1. SDI II Tx Register Summary 7.3.2. SDI II Tx Register Description 7.3.3. SDI II Rx Register Summary 7.3.4. SDI II Rx Register Description
8. SDI II IP Core Testbench and Design Examples x
8.1. Design Examples for Intel® Arria® 10, Intel® Cyclone® 10 GX, Intel® Stratix® 10, and Intel Agilex® 7 F-Tile Devices 8.2. Design Examples for Arria V, Cyclone V, and Stratix V Devices
8.1. Design Examples for Intel® Arria® 10, Intel® Cyclone® 10 GX, Intel® Stratix® 10, and Intel Agilex® 7 F-Tile Devices x
8.1.1. Design Example Presets
8.2. Design Examples for Arria V, Cyclone V, and Stratix V Devices x
8.2.1. Design Example Components 8.2.2. Design Reference 8.2.3. Simulating the SDI II IP Core Design
8.2.1. Design Example Components x
8.2.1.1. Video Pattern Generator 8.2.1.2. Transceiver Reconfiguration Controller 8.2.1.3. Reconfiguration Management 8.2.1.4. Reconfiguration Router 8.2.1.5. Avalon-MM Translators
8.2.2. Design Reference x
8.2.2.1. Video Pattern Generator Signals 8.2.2.2. Transceiver Reconfiguration Controller Signals 8.2.2.3. Reconfiguration Management Parameters 8.2.2.4. Reconfiguration Router Signals
8.2.3. Simulating the SDI II IP Core Design x
8.2.3.1. Simulation Run Time
1. SDI II IP Core Quick Reference
2. SDI II IP Core Overview
3. SDI II IP Core Getting Started
4. SDI II IP Core Parameters
5. SDI II IP Core Functional Description
6. SDI II IP Core Signals
7. SDI II IP Core Design Considerations
8. SDI II IP Core Testbench and Design Examples
9. SDI II Intel® FPGA IP User Guide Archives
10. Document Revision History for the SDI II Intel® FPGA IP User Guide

2.4. Performance and Resource Utilization

The tables below list the typical resource utilization data and the recommended speed grades for the SDI II IP core with the Intel® Quartus® Prime software.

Note: The resource utilization data was obtained by using the most common configurations for each video standard and from one specific variant of each device family.
Table 5.  Resource Utilization for Each Video Standard for Intel Agilex® 7 F-Tile Devices
Standard Active Video Data Protocols ALMs Needed Dedicated Logic Registers Block Memory Bits
HD-SDI TX None 115 125 0
HD-SDI RX None 630 897 0
3G-SDI TX None 409 400 0
3G-SDI RX None 987 1393 0
Triple Rate SDI TX None 484 515 0
Triple Rate SDI RX None 1,286 1,639 0
Multi Rate (Up to 12G-SDI) TX None 2,761 3,113 0
AXIS-VVP Full 1 5,269 6,588 698368 (37 M20K)
Multi Rate (Up to 12G-SDI) RX None 5,052 5,227 0
AXIS-VVP Full1 6,750 8,005 598784 (34 M20K)
Note: The above data was obtained by using the most common configurations for each video standard and from one specific device part for each family only.
Table 6.  Resource Utilization for Each Video Standard for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
Standard ALMs Needed Dedicated Logic Registers Block Memory Bits
HD-SDI TX 100 144 0
HD-SDI RX 532 924 0
3G-SDI TX 372 404 0
3G-SDI RX 842 1,506 0
Triple Rate TX 462 525 0
Triple Rate RX 1,082 1,807 0
Multi Rate (Up to 12G-SDI) TX 2,567 3,019 0
Multi Rate (Up to 12G-SDI) RX 4,168 5,898 0
Table 7.  Resource Utilization for Each Video Standard for Intel® Stratix® 10 Devices
Standard ALMs Needed Dedicated Logic Registers Block Memory Bits
HD-SDI TX 117 125 0
HD-SDI RX 632 883 0
3G-SDI TX 380 400 0
3G-SDI RX 981 1,378 0
Triple Rate TX 486 515 0
Triple Rate RX 1,269 1,744 0
Multi Rate (Up to 12G-SDI) TX 2,780 3,017 0
Multi Rate (Up to 12G-SDI) RX 5,124 5,951 0
Table 8.  Resource Utilization for Each Video Standard for Arria V, Cyclone V, and Stratix V Devices
Standard ALMs Needed Dedicated Logic Registers Block Memory Bits
SD-SDI TX 96 167 0
SD-SDI RX 502 693 60
HD-SDI TX 146 213 0
HD-SDI RX 542 929 0
HD Dual Link TX 452 553 0
HD Dual Link RX 1,249 2,154 4,608
3G-SDI TX 448 468 0
3G-SDI RX 863 1,449 0
Dual Rate TX 252 264 0
Dual Rate RX 930 1,348 0
Triple Rate TX 514 567 0
Triple Rate RX 1,115 1,763 0
Table 9.  Recommended Speed Grades
Device Family FPGA Fabric Speed Grade
Arria V GX/GT/SX/ST Any supported speed grade
Arria V GZ Any supported speed grade
Cyclone V –6, –7
Stratix V Any supported speed grade
Intel® Arria® 10 Any supported speed grade
Intel® Stratix® 10 Any supported speed grade
Intel® Cyclone® 10 GX Any supported speed grade
Intel Agilex® 7 F-Tile Any supported speed grade
1 Configured at Bits per color sample = 12.
Level Two Title