- 184.108.40.206. Potential Routing Problem During Fitter Stage in Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
- 220.127.116.11. Unconstrained Clocks in SDI Multi-Rate RX Using Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
- 8.1. Design Examples for Intel® Arria® 10, Intel® Cyclone® 10 GX, Intel® Stratix® 10, and Intel® Agilex™ F-tile Devices
18.104.22.168. Transceiver Reconfiguration Controller
For Arria V, Cyclone V, and Stratix V design examples, the transceiver reconfiguration controller allows you to change the device transceiver settings at any time.
Any portion of the transceiver can be selectively reconfigured. Each portion of the reconfiguration requires a read-modify-write operation (read first, then write), in such a way by modifying only the appropriate bits in a register and not changing other bits. Prior to this operation, you must define the logical channel number and the streamer module mode.
You can perform a transceiver dynamic reconfiguration in these two modes:
- Streamer module mode 1 (manual mode)—execute a series of Avalon-MM write operation to change the transceiver settings. In this mode, you can execute a write operation directly from the reconfiguration management/router interface to the device transceiver registers.
- Streamer module mode 0—use the .mif files to change the transceiver settings.
For read operation, after defining the logical channel number and the streamer module mode, the following sequence of events occur:
- Define the transceiver register offset in the offset register.
- Read the data register. Toggle the read process by setting bit 1 of the control and status register (CSR) to logic 1.
- Once the busy bit in the CSR is cleared to logic 0, it indicates that the read operation is complete and the required data should be available for reading.
For write operation, after setting the logical channel number and the streamer module mode, the following sequence of events occur:
- Define the transceiver register offset (in which the data is written to) in the offset register.
- Write the data to the data register. Toggle the write process by setting bit 0 of the CSR to logic 1.
- When the busy bit in the CSR is cleared to logic 0, it indicates that the transceiver register offset modification is successful.
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