SDI II Intel® FPGA IP User Guide

ID 683133
Date 10/21/2022

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Document Table of Contents SD-SDI Timing Jitter With External VCXO Which Receive FVH Sync Signals

In Intel® Agilex™ device family, this signal is not accurate enough to clock the external VCXO in SD-SDI mode for genlocking purpose. As a workaround, Intel recommends to use an external sync separator to generate this signal to the external VCXO. Alternatively, you can use parallel loopback without VCXO design example.

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